The goal of visual telecommunication has been to create a sense of "being there" or "telepresence." This paper introduces a novel shared drawing medium called ClearBoard that goes beyond "being there" by providing virtual shared workspace. It realizes (1) a seamless integration of shared drawing space and partner's image, and (2) eye contact to support real-time and remote collaboration by two users. We devised the key metaphor: "talking through and drawing on a transparent glass window" to design ClearBoard. A prototype, ClearBoard-1 is implemented based on the "Drafter-Mirror" architecture. This paper first reviews previous work on shared drawing support to clarify our design goals. We then examine three metaphors that fulfill these goals. The design requirements and the two possible system architectures of ClearBoard are described. Finally, some findings gained through the experimental use of the prototype, including the feature of "gaze awareness," are discussed.

It has become an important subject to realize a high-speed D/A converter with low supply voltage. This paper discusses a 10 bit 50 MS/s CMOS D/A converter with 2.7 V power supply. Reduction of the supply voltage is achieved by developing "saturation-linear" biasing technique in current sources. In this scheme, a grounded transistor in cascode configuration is biased in linear region. High conversion rate is obtained by driving this grounded transistor directly. A charging transistor is also introduced into the current source for accelerating the settling time. The D/A converter is fabricated in a 1 µm CMOS process without using optional process steps. It successfully operates at 50 MS/s with 2.7 V power supply. The circuit techniques discussed here can be easily introduced into half-micron D/A converters.

A group-based random access communication system which consists of two groups of many users is considered. The two different groups share a common random multiple access channel. Users from a group are allocated a high transmitting power level and have a high probability of correct reception among overlapping packets. We set a threshold, θ, which is such that the group with the high power level will occupy the channel if less than or equal to θ packets are transmitted from the group with the low power level. We obtain a two-dimensional Markovian model by tracing the number of backlogged users in the two groups. The two-dimensional Markov chain is shown to be not ergodic and thus the system is not stable. A two-dimensional retransmission algorithm is developed to stabilize the system and the retransmission control parameters are chosen so as to maximize the channel throughput. An equilibrium point analysis is performed by studying the drift functions of the system backlog and it is shown that there is a unique global equilibrium point. The channel capacity for the system is found to be in the range from 0.47 up to 0.53, which is a remarkable increase compared to the conventional slotted ALOHA system.

In this paper, we provide an efficient algorithm for GMD (Generalized Minimum Distance) decoding of BCH codes over q-valued logic, when q is pl (p: prime number, l: positive integer). An algebraic errors-and-erasures decoding procedure is required to execute only one time, whereas in a conventional GMD decoding at mostd/2algebraic decodings are necessary, where d is the design distance of the code. In our algorithm, Welch-Berlekamp's iterative method is efficiently employed to reduce the number of algebraic decoding procedures. We also show a method for hardware implementation of this GMD decoding based on q-valued logic.

Various models of a neuron have been proposed and many studies about them and their networks have been reported. Among these neurons, this paper describes a study about the model of a neuron providing its own feedback input and possesing a chaotic dynamics. Using a return map or a histogram of laminar length, type-I intermittency is recognized in a recurrent neuron and its network. A posibility of controlling dynamics in recurrent neural networks is also mentioned a little in this paper.

This paper discusses psychophysical aspects of human sensory system through a differential-geometrical formulation. The discussions reveal relationships among three fundamental functions--the psychophysical, the DL and the JND functions, which characterize sensory system.

Under the conditions of Poisson arrivals and single copy transmission, we designed a minimum delay protocol for packet satellite communications. The approach is to assume a hybrid random-access/reservation protocol, derive its average delay and minimize the delay with respect to all tunable system parameters. We found that for minimum average delay,1) a spare reservation should normally but not always be made for each packet transmission.2) all unreserved slots (i.e. Aloha slots) should be filled with a packet rate of one per slot whenever possible. In other words, the utilization of Aloha slots should be maximized.3) an optimum balance between transmitting packets and making reservations before transmission should be maintained.

Recently, fuzzy logic which is a kind of infinite multiple-valued logic has been studied to treat certain ambiguities, and its algebraic properties have been studied by the name of fuzzy logic functions. In order to treat modality (necessity, possibility) in fuzzy logic, which is an important concept of multiple-valued logic, the intuitionistic logical negation is required in addition to operations of fuzzy logic. Infinite multiple-valued logic functions introducing the intuitionistic logical negation into fuzzy logic functions are called Kleene-Stone logic functions, and they enable us to treat modality. The domain of modality in which Kleene-Stone logic functions can handle, however, is too limited. We will define α-KS logic functions as infinite multiple-valued logic functions using a unary operation instead of the intuitionistic logical negation of Kleene-Stone logic functions. In α-KS logic functions, modality is closer to our feelings. In this paper we will show some algebraic properties of α-KS logic functions. In particular we prove that any n-variable α-KS logic function is determined uniquely by all inputs of 7 values which are 7 specific truth values of the original infinite truth values. This means that there is a bijection between the set of α-KS logic functions and the set of 7-valued α-KS logic functions which are restriction of α-KS logic functions to 7 specific truth values. Finally, we show a necessary and sufficient condition for a 7-valued logic function to be a 7-valued α-KS logic function.

This paper proposes a self frequency preset (SFP) PLL synthesizer to realize a simple frequency preset PLL synthesizer with temperature-resistant and shorter frequency settling time than the conventional temperature un-compensated phase and frequency preset (PFP) PLL synthesizer. Since the proposed synthesizer employs a simple frequency locked loop (FLL) circuit to preset the output frequency at each frequency hopping period, the synthesizer eliminates the need to store f-V characteristic of the VCO in ROM. The frequency settling time of the proposed synthesizer is theoretically and experimentally analyzed. The theoretical analysis using the realistic f-V characteristic of a IF band VCO show that the frequency settling time of the proposed synthesizer is 130µs shorter than that of the conventional PFP PLL synthesizer at 40MHz hopping in the 200MHz band for all temperatures. Furthermore, the experimental results confirm that the frequency acquisition time of a prototype FLL circuit is accordant with the calculated results. Thus, the proposed SFP PLL synthesizer can achieve faster frequency settling than the conventional PFP PLL synthesizer for all temperatures and its simple configuration allows to be easily implemented with existing CMOS ASIC devices.

This paper addresses onboard processing architecture employing direct regeneration. The advantage of direct regeneration is its hardware simplicity, even though the bit error rate performance is slightly inferior to that of demodulation-remodulation scheme with coherent detection. The channel filtering schemes as well as achievable capacities are examined by computer simulation. It is found that the system with direct regeneration has advantage in channel capacity and transmit earth station e.i.r.p. for small earth stations. A possible configuration of direct regeneration onboard in future satellite systems is proposed.

Process and device technologies of CMOS devices for low-voltage operation are described. First, optimum power-supply voltage for CMOS devices is examined in detail from the viewpoints of circuit performance, device reliability and power dissipation. As a result, it is confirmed that power-supply voltage can be reduced without any speed loss of the CMOS device. Based upon theoretical understanding, the author suggests that lowering threshold voltage and reduction of junction capacitance are indispensable for CMOS devices with low-voltage supply, in order to improve the circuit performance, as expected from MOS device scaling. Process and device technologies such as Silicon On Insulator (SOI) device, low-temperature operation and CMOS Shallow Junction Well FET (CMOS-SJET) structure are reviewed for reduction of the threshold voltage and junction capacitance which lead to high-seed operation of the COMS device at low-voltage.

In this paper, we are concerned with a problem of obtaining an approximate solution of a finite-dimensional nonlinear equation with guaranteed accuracy. Assuming that an approximate solution of a nonlinear equation is already calculated by a certain numerical method, we present computable conditions to validate whether there exists an exact solution in a neighborhood of this approximate solution or not. In order to check such conditions by computers, we present a method using rational arithmetic. In this method, both the effects of the truncation errors and the rounding errors of numerical computation are taken into consideration. Moreover, based on rational arithmetic we propose a new modified Newton interation to obtain an improved approximate solution with desired accuracy.

This paper describes high speed circuit techniques for 1 to 5 V operating memories, with special emphasis on SRAM. For achieving large supply voltage margin and high speed compatibly, two novel circuit schemes are proposed; one is Switched Delay Line Pulse Generator (SDLPG), which is a new Address Transition Detect (ATD) pulse generating scheme and the other is Resistor Inserted Current mirror Sense Amplifier (RICSA). In this scheme, critical path of ATD pulse is switched between CR delay line and CMOS gate delay line depending on supply voltage. As a result, ATD pulse width can be tuned to be dominated by CR delay line propagated pulse at high Vcc region and by CMOS gate chain propagated one at low Vcc region. In SDLPG Vcc dependence of ATD pulse width can be adjusted to minimum value for stable operation at both low and high end of target operating voltage region, which leads to high-speed memory operation without excess ATD pulse width. RICSA is a simple circuit scheme modifying current mirror sense amplifier with current limitting resistor inserted between the common source node of two driver NMOSFETs and the drain node of the switch NMOSFET. This technique inproves poor sensitivity of conventional current mirror sense amplifier when common mode input voltage near Vcc is applied, which offers a suitable sense amplifier for 15 V operating SRAM. By applying these techniques and 1 V operating cell techniques, SRAM with high-speed operation in 1 to 5 V range is realized. They are also applicable for other low-voltage memories such as DRAM and EPROM.

This paper describes a monolithic 10-b A/D converter that realized a maximum conversion frequency of 300 MHz. Through the development of the interpolated-parallel scheme, the severe requirement for the transistor Vbe matching can be alleviated drastically, which improves differential nonlinearity (DNL) significantly to within 0.4 LSB. Furthermore, an extremely small input capacitance of 8 pF can be attained, which translates into better dynamic performance such as SNR of 56 dB and THD of 59 dB for an input frequency of 10 MHz. Additionally, the folded differential logic circuit has been developed to reduce the number of elements, power dissipation, and die area drastically. Consequently, the A/D converter has been implemented as a 9.0 4.2-mm2 chip integrating 36K elements, which consumes 4.0 W using a 1.0-µm-rule, 25-GHz ft, double-polysilicon self-aligned bipolar technology.

The mechanism of environment-dependent self-organization of "positional information" in a coupled nonlinear oscillator system is proposed as a new principle of realtime coordinative control in biological distributed system. By modeling the pattern formation in tactic response of Physarum plasmodium, it is shown that a global phase gradient pattern self-organized by mutual entrainment encodes not only the positional relationship between subsystems and the total system but also the relative relationship between internal state of the system and the environment.

The purpose of this paper is to offer a modal logic which enables us symbolic reasoning about data, especially, fuzzy relations. For such a purpose, the present author provided some systems of modal fuzzy logic. As a continuous one of those previous works, a logic based on the graded modalities is proposed. After showing some properties of this logic, the decision procedure for this logic is given in the rectangle method.

A non-profit satellite communication network is desired to be configured by using low cost earth stations in the field of education, research and health in the Pacific region. This paper proposes the following concept as one of the tools to realize such a network: (a) A hitchhiker transponder dedicated to the network, and (b) The volunteer group prepares earth stations. A preliminary system design shows that the S band hitchhiker payload is most appropriate and has the weight of about 3kg. The feasibility of manufacturing earth stations by a volunteer group is examined through the experiment using ETS-V satellite. The parameters of the hitchhiker payload are re-examined on the basis of the experience of the experiment.

A new optimal nonlinear regulator design method is developed by applying a multi-layered neural network and a fixed point theorem for a nonlinear controlled system. Based on the calculus of variations and the fixed point theorem, an optimal control law containing a nonlinear mapping of the state can be derived. Because the neural network has not only a good learning ability but also an excellent nonlinear mapping ability, the neural network is used to represent the state nonlinear mapping after some learning operations and an optimal nonlinear regulator may be formed. Simulation demonstrates that the new nonlinear regulator is quite efficient and has a good robust performance as well.

In this paper, a synthesizing method is proposed for the design of discrete-time cellular neural networks for binary image processing. Based on the theory of digital-logical design paradigm of threshold logic, the template parameters of the discrete-time cellular neural network for a prescribed binary image processing problem are calculated. Application examples including edge detection, connected component detection, and hole filling are given to demonstrate the merits and limitations of the proposed method. For a given realization of the parameters of the cloning template, a guideline for the selection of the offset Ic for maximum error tolerance is also considered.

A low-voltage, high-speed 4-bit CMOS single chip microprocessor, with instruction execution time of 1.0µs at a power supply voltage of 1.8V, has been developed. A single chip processor generally includes crystal oscillation circuits to generate a system clock or a time-base clock. But when the operating voltage is lowered, it becomes difficult to get oscillations to start reliably and to continue stably. This paper describes a low voltage circuit design method for built-in crystal oscillators. Simple design equations for oscillation starting voltage and oscillation starting time are introduced. Then effects of the circuit device parameters, such as power supply voltage, loop gain values, and subthreshold swing S, on the low voltage performance of the crystal oscillators are considered. It is shown that the crystal oscillators operate in a tailing (subthreshold) region at voltages lower than about 1.8 V. Subthreshold swing, threshold voltage, and open loop gain have a significant influence on low voltage oscillation capability. This design method can be applied to crystal oscillators for a wide range of operating voltages.