BiCMOS circuit performance at low supply voltages is discussed. The basic advantages of BiCMOS circuits are briefly reviewed, and then actual advantages of the BiCMOS gate and the BiCMOS sense circuits, which are typical BiCMOS circuits, are explained. Their advantages at low supply voltages are also discussed. BiCMOS gates, BiCMOS sense circuits, and combined circuits that include a BiCMOS sense circuit are two or three times faster than CMOS circuits down to a supply voltage of 2 V. BiCMOS circuits have high performance even at low supply voltages such as 2 V.

By adding a linear resistor in series with the inductor in Chua's circuit, we obtain a circuit whose state equation is topologically conjugate (i.e., equivalent) to a 21-parameter family C of continuous odd-symmetric piecewise-linear equations in R3. In particular, except for a subset of measure zero, every system or vector field belonging to the family C, can be mapped via an explicit non-singular linear transformation into this circuit, which is uniquely determined by 7 parameters. Since no circuit with less than 7 parameters has this property, this augmented circuit is called an unfolding of Chua's circuit--it is analogous to that of "unfolding a vector field" in a small neighborhood of a singular point. Our unfolding, however, is global since it applies to the entire state space R3. The significance of the unfolded Chua's Circuit is that the qualitative dynamics of every autonomous 3rd-order chaotic circuit, system, and differential equation, containing one odd-symmetric 3-segment piecewise-linear function can be mapped into this circuit, thereby making their separate analysis unnecessary. This immense power of unification reduces the investigation of the many heretofore unrelated publications on chaotic circuits and systems to the analysis of only one canonical circuit. This unified approach is illustrated by many examples selected from a zoo of more than 30 strange attractors extracted from the literature. In addition, a gallery of 18 strange attractors in full color is included to demonstrate the immensely rich and complex dynamics of this simplest among all chaotic circuits.

Asynchronous machines are a topic of great interest in the research area of actuators. Due to the complexity of these systems and to the required performance, the modelling and control of asynchronous machines are complex questions. Problems arise when the control goals require accurate descriptions of the electric machine or when we need to identify some electrical parameters; in the models employed it becomes very hard to take into account all the phenomena involved and therefore to make the error amplitude adequately small. Moreover, it is well known that, though an efficient control strategy requires knowledge of the flux vector, direct measurement of this quantity, using ad hoc transducers, does not represent a suitable approach, because it results in expensive machines. It is therefore necessary to perform an estimation of this vector, based on adequate dynamic non-linear models. Several different strategies have been proposed in literature to solve the items in a suitable manner. In this paper the authors propose a neural approach both to derive NARMAX models for asynchronous machines and to design non-linear observers: the need to use complex models that may be inefficient for control aims is therefore avoided. The results obtained with the strategy proposed were compared with simulations obtained by considering a classical fifth-order non-linear model.

This paper presents an optimization method for pseudo-Kronecker expressions of p-valued input two-valued output functions by using multi-place decision diagrams for p2 and p4. A conventional method using extended truth tables requires memory of O (3n) to simplify an n-variable expression, and is only practical for functions of up to n14 variables when p2. The method presented here utilizes multi-place decision diagrams, and can optimize considerably larger problems. Experimental results for up to n39 variables are shown.

A priori estimation is presented for a computational complexity of the homotopy method applying to a certain class of strongly monotone nonlinear equations. In the present papers, a condition is presented for a certain class of uniquely solvable equations, under which an upper bound of a computational complexity of the Newton type homotopy method can be a priori estimated. In this paper, a condition is considered in a case of linear homotopy equations including the Newton type homotopy equations. In the first place, the homotopy algorithm based on the simplified Newton method is introduced. Then by using Urabe type theorem, which gives a sufficient condition guaranteeing the convergence of the simplified Newton method, a condition is presented under which an upper bound of a computational complexity of the algorithm can be a priori estimated, when it is applied to a certain class of strongly monotone nonlinear equations. The presented condition is demonstrated by numerical experiments.

The paper considers multiple-valued logic systems having the property that the ambiguity of the system increases as the ambiguity of each component increases. The partial-ordering relation with respect to ambiguity with the greatest element 1/2 and minimal elements 0, 1 or simply the ambiguity relation is introduced in the set of truth values V {0, 1/ (p1), , 1/2, , (p2) / (p1), 1}. A-monotonic p-valued logic functions are defined as p-valued logic functions monotonic with respect to the ambiguity relation. A necessary and sufficient condition for A-monotonic p-valued logic functions is presented along with the proofs, and their logic formulae using unary operators defined in the ambiguity relation are given. Some discussions on the extension of theories to other partial-ordering relations are also given.

Design of locally computable combinational circuits is a very important subject to implement high-speed compact arithmetic and logic circuits in VLSI systems. This paper describes a multiple-valued code assignment algorithm for the locally computable combinational circuits, when a functional specification for a unary operation is given by the mapping relationship between input and output symbols. Partition theory usually used in the design of sequential circuits is effectively employed for the fast search for the code assignment problem. Based on the partition theory, mathematical foundation is derived for the locally computable circuit design. Moreover, for permutation operations, we propose an efficient code assignment algorithm based on closed chain sets to reduce the number of combinations in search procedure. Some examples are shown to demonstrate the usefulness of the algorithm.

An idea of optimal output permutation of multiple-valued sum-of-products expressions is presented. The sum-of-products involve the TSUM operator on the MIN of window literal functions. Some bounds on the maximum number of implicants needed to cover an output permuted function are clarified. One-variable output permuted functions require at most p1 implicants in their minimal sum-of-products expressions, where p is the radix. Two-variable functions with radix between three and six are analyzed. Some speculations of maximum number of the implicants could be established for functions with higher radix and more than 2-variables. The result of computer simulation shows that we can have a saving of approximately 15% on the average using permuting output values. Moreover, we demonstrate the output permutation based on the output density as a simpler method. For the permutation, some speculation is shown and the computer simulation shows a saving of approximately 10% on the average.

This paper presents Bi-CMOS current-mode multiple valued logic circuit with 1.5 V supply voltage. This circuit is composed of current mirror, threshold detector and current source. This circuit has advantages such as high accuracy, high speed, high density and low supply voltage. So, it is possible to realize high-radix multiple valued logic circuit. As an other application of the proposed circuit, a processing unit of fuzzy inference is given. This circuit operates with high speed and high accuracy. The circuit simulation of the proposed circuit has been performed using SPICE2 program.

The Consultative Committee of Space Data Systems (CCSDS) proposes a packetized telemetry scheme for the convenience of data exchange and networking in space activity. This paper describes the outline of the telemetry scheme and the on-orbit experiment which was carried out to show the applicability of the proposed CCSDS packet telemetry scheme using the Japan's satellite "Hiten" in a highly elliptical orbit. The telemetry data which are generated by the onboard instruments are packetized in Hiten, and reformed to the original data in earth stations successfully. The experimental results show that the standardized scheme is helpful for tracking cross-support between organizations, and that the concatenated code is quite effective to transmit data in a low C/N condition.

Generally it is said that a fuzzy control system has fault tolerant properties, but it is not clearly studied. In this paper, first, the influence of faults in fuzzy control systems is examined. Errors given by fault simulation are not negligible. However, no fault detecting method is applied in the realized fuzzy control systems. Then a fault-checking method to detect faults is proposed in this paper.

In the direct product space of a complete metric linear space X and its related space Y, a fuzzy mapping G is introduced as an operator by which we can define a projective fuzzy set G(x,y) for any xX and yY. An original system is represented by a completely continuous operator f(x)Y, e.g., in the form x=λ(f(x)), (λ is a linear operator), and a nondeterministic or fuzzy fluctuation induced into the original system is represented by a generalized form of system equation xβG(x,f(x)). By establishing a new fixed point theorem for the fuzzy mapping G, the existence and evaluation problems of solution are discussed for this generalized equation. The analysis developed here for the fluctuation problem goes beyond the scope of the perturbation theory.

Abrupt variations of attractors caused by argumental discreteness in non-Hermitian complex-valued neural networks are reported. When we apply the complex-valued associative memories to dynamical processing, the weighting matrices are constructed as non-Hermitian in general so that they have motive force to the signal vectors. It is observed that competitions between argumental rotation force and noise-suppression ability of associative memories lead to trajectory distortions and abrupt variations of the attractors.

In this paper, a new time series analysis method is proposed. The proposed method uses the exponential (EXP) model. The residual signal is assumed to be identically and independently distributed (IID). To achieve accurate and efficient estimates, the parameter of the system model is calculated by maximizing the logarithm of the likelihood of the residual signal which is assumed to be IID t-distribution. The EXP model theoretically assures the stability of the system. This model is appropriate for analyzing signals which have not only poles, but also poles and zeroes. The asymptotic efficiency of the EXP model is addressed. The optimal solution is calculated by the Newton-Raphson iteration method. Simulation results show that only a small number of iterations are necessary to reach stationary points which are always local minimum points. When the method is used to estimate the spectrum of synthetic signals, by using small α we can achieve a more accurate and efficient estimate than that with large α. To reduce the calculation burden an alternative algorithm is also proposed. In this algorithm, the estimated parameter is updated in every sampling instant using an imperfect, short-term, gradient method which is similar to the LMS algorithm.

It is shown from a computer analysis that there exists a resonant mode of a surface wave which propagates along Goubau line, and that the attenuation of such a mode is very low. The approximate formula for obtaining the resonant frequency is also given.

This paper describes the potential of KrF excimer laser lithography for the development and production of 64 M and 256 Mbit DRAMs on the basis of our recent developed results. Quarter micron KrF excimer laser lithography has been developed. A new chemically amplified positive resist realizes high stability and process compatibility for 0.25 micron line and space patterns and 0.35 micron contact hole patterns. This developed resist is characterized as the increase of dissolution characteristics in exposed areas, and hence means the high resolution is obtained. A multiple interference effect was greatly reduced by using our over coat film or anti-reflective coating. This over coat film has no intermixing to the resist and it is simultaneously removed when the resist is developed. This anti-reflective coating has low etch selectivity to the resist, and hence the over coat film is etched away when etching the substrate. The two major results indicate that the KrF excimer laser lithography is promising for the development of 256 MDRAMs.

Selective epitaxial growth technology has been extended to the base formation of a transistor on the basis of the SATURN (Self-Alignment Technology Utilizing Reserved Nitride) process, a high-speed bipolar LSI processing technology. The formation of a self-aligned base contact, coupled with SIC (Selective Ion-implanted Collector) fabricated by lowenergy ion implantation, has not only narrowed the transistor active regions but has drastically reduced the base width. A final base width of 800 and a maximum cut-off frequency of 31 GHz were achieved.

A CMOS design to achieve high drivability is examined for lower power supply voltage in 0.5 µm ULSI. The design consists of two points. (1) A very narrow (50 nm) sidewall is used to achieve high drivability and also to obtain hot-carrier-reliability. (2) A retrograded channel profile with NMOS and PMOS is designed to achieve high drivability and also to reduce short channel effect. It is shown that the propagation delay times (tpd) of a unloaded Inverter and a loaded 2-way NAND gate are improved 30% with the newly designed CMOS, compared with the conventionally designed CMOS. It is also proved that the tpd keeps the scaling trend of the previous-5 V-era even in 3.3 V-era by adapting the newly designed CMOS. Moreover, 7.1 ns multiplication time of 1616-bit multiplier is obtained under 0.5 µm design rule.

In this paper, we discuss secure protocols for shared computation of algorithms associated with digital signature schemes based on discrete logarithms. Generic solutions to the problem of cooperatively computing arbitraty functions, though formally provable according to strict security notions, are inefficient in terms of communication--bits and rounds of interaction--; practical protocols for shared computation of particular functions, on the other hand, are often shown secure according to weaker notions of security. We propose efficient secure protocols to share the generation of keys and signatures in the digital signature schemes introduced by Schnorr (1989) and ElGamal (1985). The protocols are built on a protocol for non-interactive verifiable secret sharing (Feldman, 1987) and a novel construction for non-interactively multiplying secretly shared values. Together with the non-interactive protocols for shared generation of RSA signatures introduced by Desmedt and Frankel (1991), the results presented here show that practical signature schemes can be efficiently shared.

Practical linewidth measurement accuracy better than 0.02 µm 3 sigma that meets the production requirement for devices with sub-half micron features, was achieved in a field emission scanning electron-beam metrology system (Hitachi S-7000). In order to establish high accuracy linewidth measurement, it was found in the study that reduction of electron-beam diameter and precise control of operating conditions are significantly effective. For the purpose of reducing electron-beam diameter, a novel electron optical system was adopted to minimize the chromatic aberration which defines electron-beam profile. As a result the electron beam diameter was reduced from 20 nm to 16 nm. In order to reduce measurement uncertainties associated with actual operating conditions, a field emission electron gun geometry and an objective lens current monitor were investigated. Then the measurement uncertainties due to operating conditions was reduced from 0.016 µm to 0.004 µm.