In this study, an expression of the regression relationship with less information loss is concretely derived in the form suitable to the existence of amplitude constraint of the observed data and the prediction of response probability distribution. The effectiveness of the proposed method is confirmed experimentally by applying it to the actual acoustic data.

In this paper, we investigate various technology aspects in fiber-to-the-microcell systems. Background studies on radio propagation environment and system operations are provided first. The fundamental linearity characteristics of a directly and externally modulated optical links are analyzed next. An overall comparison between the two types of optical links, and system requirements among all types of wireless systems (from macrocells to picocells) are presented. Future research and development directions are also suggested.

A novel approximate equivalent edge currents (EECs) are proposed for use in the modified edge representation (MER) for flat plates. It was reported that PO-EECs with classical PO diffraction coefficients, as applied to MER, perfectly recover PO surface integration. The inclusion of classical FW-EECs as it is, however, would not enhance the accuracy since the reality of the fringe wave is lost in the edge modification. This paper presents simple approximation for inclusion of FW-EECs in MER; FW-EECs are weighted by the function of the angle between the modified edge and the real edge. The key feature of this approach is that uniform fields are predicted everywhere though only classical diffraction coefficients are used. MER also simplifies the ray-tracing in the secondary diffraction analysis. Numerical results for diffraction from flat plates demonstrate the potential of these EECs.

A complete analysis for the quantization noises and the reconstruction noises of the wavelet pyramid coding system is given. It is shown that in the (orthonormal) wavelet image coding system, there exists a simple and exact formula to compute the reconstruction mean-square-error (MSE) for any kind of quantization errors. Based on the noise analysis, an optimal bit allocation scheme which minimizes the system reconstruction distortion at a given rate is developed. The reconstruction distortion of a wavelet pyramid system is proved to be directly proportional to 2-2, where is a given bit rate. It is shown that, when the optimal bit allocation scheme is adopted, the reconstruction noises can be approximated to white noises. Particularly, it is shown that with only one known quantization MSE of a wavelet decomposition at any layer of the wavelet pyramid, all of the reconstruction MSE's and the quantization MSE's of the coding system can be easily calculated. When uniform quantizers are used, it is shown that at two successive layers of the wavelet pyramid, the optimal quantization step size is a half of its predecessor, which coincides with the resolution version of the wavelet pyramid decomposition. A comparison between wavelet-based image coding and some well-known traditional image coding methods is made by simulations, and the reasons why the wavelet-based image coding is superior to the traditional image coding are explained.

This letter discusses a behavior of solitons in a Josephson junction transmission line which is described by a perturbed sine-Gordon equation. It is shown that a soliton wave leads a quasi-periodic break down route to chaos in a Josephson transmission line. This route show phase locking, quasi-periodic state, chaos and hyper chaos, and these phenomena are examined by using Poincar sections, circle map, rotation number, and so on.

Logic synthesizers usually have good area minimization capabilities, producing circuits of minimal area. But good delay minimization techniques are still missing in current logic synthesis technology. In [7], the RENO algorithm (which stands for REsynthesis for Network Optimization) was proposed for minimizing the area of multi-level combinational networks, and its effectiveness in designing minimal-area networks has been demonstrated. In this paper, we present improvements and extensions of the RENO algorithm for network delay minimization by using Boolean resynthesis techniques. We will discuss new algorithms for gate resynthesis which have not only reduced the processing time significantly, but also have improved the quality of minimization. Due to the generality of the gate resynthesis algorithms, we can minimize both delay and area of a network concurrently in a unified way, and network delay is reduced significantly with no or very small area penalty. Extensive experimental results and comparison with the speed_up algorithm in SIS-1.0 are presented.

Acceleration techniques have been incorporated into the generalized method of characteristics (GMC) to perform transient analysis of uniform transmission lines, for the special case when the transmission lines are driven by digital signals. These techinques have been proved to improve the simulation speed to a great extent when the analysis is carried out using iterative waveform relaxation method. It has been identified that the load impedance connected to the transmission line has a bearing on the efficiency of one of these acceleration techniques. Examples of an RLCG line terminated with linear loads as well as nonlinear loads are given to illustrate the advantage of incorporating these acceleration techniques.

Reducing communication complexity is a viable approach to multilevel logic synthesis. A communication complexity based approach was proposed previously. In the previous works, only disjoint input decomposition was considered. However, for certain types of circuits, the circuit size can be reduced by using overlapped decomposition. In this paper, we consider overlapped decompositions. Some design issues for overlapped decompositions such as detecting globals" and deriving subfunctions are addressed. Moreover, the Decomposition Don't Cares (DDC) is considered for improving the decomposed results. By using these techniques together, the area and delay of circuits can be further minimized.

System and chip synthesis must evaluate candidate Register-Transfer (RT) architectures with respect to finished physical designs. Current RT level cost measures, however, are highly simplified and do not reflect the real physical disign. Complete physical design, on the other hand, is quite costly, and infeasible to be iterated many times. In order to establish a more realistic assessment of layout effects, we propose a new layout model which efficiently accounts for the effects of wiring and floorplanning on the area and performance of RT level designs, before the physical design process. Benchmarking has shown that our model is quite accurate.

We introduce automatic procedures for generating and verifying sufficient correctness properties of synchronous processors. The targeted circuits are synchronous array processors designed from localized, highly regular data dependency graphs (DDGs). The specification, in the form of a DDG, is viewed as a maximally parallel circuit. The implementation, on the other hand, is a (partially) serialized circuit. Since these circuits are not equivalent from an automata-theoretic viewpoint, we define the correctness of the implementation against the specification to mean that a certain relation (called the β-relation) holds between the two. We use a compositional approach to decouple the verification of the control circuitry from that of the data path, thereby gaining efficiency. An array processor in isolation may not have a definite flow of control, because control may reside in the data stream. Therefore, for the purpose of verification, we construct an auxiliary machine, which keeps a timing reference and generates control signals abstracted from a typical data stream. Sufficient correctness conditions are expressed as past-tense computation tree logic (CTL) formulae and verified by CTL model-checking procedures. Experimental results of the verification of a matrix multiplication array and a Gaussian elimination array are presented.

In this paper, a new method of synthesizing multi-level logic circuits directly from binary decision diagrams (BDDs) is proposed. In the simple multiplexer implementation, the depth of the synthesized circuit was always O (n), where n is the number of input variables. The new synthesis method attempts to reduce the depth of circuits. The depth of the synthesized circuits is O (log n log w) where w is the maximum width of given BDDs. The synthesized circuits are 2-rail-input 2-rail-output logic circuits. The circuits have good testability; it is proved that the circuits are robustly path-delay fault testable and also totally self-checking for single stuck-at faults.

Fiber-optic microcellular system has been studied actively as an excellent system for solving the equipment cost problems in microcellular systems. However, the occurrence of intermodulation distortion (IMD) arising from the nonlinearity of the laser diode used for E/O conversion which degrades the transmission quality is a serious problem in this system. In this paper, we propose a new frequency switching/IM3 reduction method, which dynamically reassigns the carrier frequencies to minimize the carrier to IMD power ratio under the hostile environment with time-varying received carrier strength, and analyze the performance improvements by the proposed method. The improvements obtained both for the worst value of the overall CNR and for the overall CNR in a specific user are numerically made clear. It is also shown that if the interval between frequency reassignings is set less than one second, a sufficient improvement in the overall CNR is achievable.

Fiber-optic passive double star (PDS) network is described as an access network for microcellular radio communication systems. The intrinsic characteristics of the PDS network, reduction in the optical fiber count and flexible access capability, are examined. A unit cell structure is introduced which enables the PDS network to be effectively incorporated into the access portion of microcellular radio communication systems. The reduced total fiber length in the unit cell structure based on the PDS network is discussed in comparison with the conventional architecture. Calculations show that there is an optimum splitting ratio that minimizes the total fiber length. When the microcell radius and service area radius are 100m and 10km, respectively, the total fiber length of the PDS network is reduced to only about 9% of that of the conventional single star (SS) network for a splitting ratio of 34. Resource sharing and handover between microcells in a unit cell are performed by using the dynamic channel allocation function of the PDS system. Substantial performance improvement for loaded traffic can be obtained by resource sharing. When the splitting ratio is 32, the available traffic of a base station (BS) increases from 0.9 [erl/BS] to 3.4 [erl/BS] by adopting dynamic channel allocation for the lost call probability of 0.01.

The value distribution of the partial autocorrelation of periodic sequences is important for the evaluation of the sequence performances when sequences of long period are used. But it is difficult to find the exact value distribution of the autocorrelation in general. Therefore we derived some properties of the partial autocorrelation for binary m-sequences which may be used to find the exact value distribution.

A new method by which images are coded with predictable and controllable subjective picture quality in the minimum cost of bit rate is developed. By using wavelet transform, the original image is decomposed into a set of subimages with different frequency channels and resolutions. By utilizing human contrast sensitivity, each decomposed subimage is treated according to its contribution to the total visual quality and to the bit rate. A relationship between physical errors (mainly quantization errors) incurred in the orthonormal wavelet image coding system and the subjective picture quality quantified as the mean opinion score (MOS) is established. Instred of using the traditional optimum bit allocation scheme which minimizes a distortion cost function under the constraint of a given bit rate, we develop an "optimum visually weighted noise power allocation" (OVNA) scheme which emphasizes the satisfying of a desired subjective picture quality in the minumum cost of bit rate. The proposed method enables us to predict and control the picture quality before the reconstruction and to compress images with desired subjective picture quality in the minimum bit rate.

In this paper, a definitce relation between the TSP's optimal solution and the attracting region in the parameters space of TSP's energy function is discovered. An many attracting region relating to the global optimal solution for TSP is founded. Then a neural network algorithm with the optimized parameters by using Orthogonal Array Table Method is proposed and used to solve the Travelling Salesman Problem (TSP) for 30, 31 and 300 cities and Map-coloring Problem (MCP). These results are very satisfactory.

The Princeton University Behavioral Synthesis System (PUBSS) performs high-level synthesis on communicating processes. The compiler accepts models written in a subset of VHDL, but performs synthesis using a more specialized model, the behavior FSMs (BFSMs), for synthesis. The simulation semantics of VHDL presents challenges in describing behavior without overly constraining that behavior solely to make the simulation work. This paper describes mismatch between the simulation semantics provided by VHDL and the synthesis semantics required for high-level synthesis and describes how we solved these problems in PUBSS.

We present algorithms for the optimization of sequential synchronous digital circuits using structural model, i.e. interconnections of combinational logic gates and synchronous registers. This approach contrasts traditional methods using state diagrams or transition tables and leveraging state minimization and encoding techniques. In particular, we model circuits by synchronous logic networks, that are weighted multigraphs representing interconnections of gates implementing scalar combinational functions. With this modeling style, area and path delays are explicit and their variation is easy to compute when circuit transformations are applied. Sequential logic optimization may target cycle-time or area minimization, possibly under area or cycle-time constraints. Optimization is performed by a sequence of transformations, directed to the desired goal. This paper describes the fundamental mechansms for transformations applicable to sequential circuits. We review first retiming and peripheral retiming techniques. The former method optimizes the position of the registers, while the latter repositions the registers to enlarge maximally the combinational region where combinational restructuring algorithms can be applied. We consider then synchronous algebraic and Boolean transformations, that blend combinational transformations with local retiming. Both classes of transformations require the representation of circuits by means of logic expressions with labeled variables, the labels representing discrete time-points. Algebraic transformations entail manipulation of time-labeled expressions with algebraic techniques. Boolean transformations exploit the properties of Boolean algebra and benefit from the knowledge of don't care conditions in the search for the best implementation of local functions. Expressing don't care conditions for sequential circuits is harder than for combinational circuits, because of the interaction of variables with different time labels. In addition, the feasibility of replacing a local function with another one may not always be verified by checking for the inclusion of the induced perturbation in local explicit don't care set. Indeed, the behavior of sequential circuits, that can be described appropriately by the relation between input and output traces, may require relational models to express don't care conditions. We describe a general formalism for sequential optimization by Boolean transformations, where the don't care conditions are expressed implicitly by synchronous recurrence equations. We present then an optimization method for this model, that can exploit degrees of freedom in optimization not possible for other methods, and hence providing solutions of possible superior quality. We conclude by summarizing the major features and limitations of optimization methods using structural models.

This paper presents two new maximum likelihood decoding (MLD) algorithms for linear codes over Z-channel, which are much more efficient than conventional exhaustive algorithms for high rate codes. In the proposed algorithms, their complexities are reduced by employing the projecting set Cs of the code, which is determined by the "projecting" structure of the code. Space and computational complexities of algorithms mainly depend upon the size of Cs which is usually several times smaller than the total number of codewords. It is shown that the upper bounds on computational complexities of decoding algorithms are in proportion to the number of parity bits and the distance between an initial estimate of the codeword and the received word, respectively, while space complexities of them are equal to the size of Cs. Lastly, numerical examples clarify the average computational complexities of the proposed algorithms, and the efficiency of these algorithms for high rate codes is confirmed.

Let U denote a set comprising elements called "keys." The goal of the nearest point problem is to search quickly for a key among some keys x1 , xn that is the nearest to a reference key x under a partial order relation defined as (x, y) (x, z) for x, y, zU if d(x, y)d(x, z) given a wide-sense distance measure d. This article proposes a method of rearranging x1 , xn into a binary perfectly-balanced tree for solving quickly the nearest point problems. Further, computational performances of the proposed method are evaluated experimentally.