This paper reviews the potential possibility and present status of trans-polyacetylene research toward realization of soliton molecular devices utilizing characteristics of the quasi-one-dimensional conductor. Properties of solitons in polyacetylene are summarized from a point of view to produce a new microelectronics beyond Si-LSI's. The limiting performance of soliton LSI's are roughly estimated. One bit information is stored in only 420 2. The information transmission rate of a wiring is 2104 Gb/s. The delay time per gate is 0.05 ps. For realization of this high performance devices, a lot of research must be carried out in future. A new circuit with new principles of operations must be developed to achieve the performance, where a localized soliton or a localized group of solitons are treated. Some systems, which may lead to development of logic circuits, are proposed. The problems in crystal quality and fabrication process are also discussed and some means against them are presented.

Japan's PARTNERS Project, one of the programmes of ISY advocated by UN, has just started. This letter is a brief introduction of the trials being carried out by the partners in the University of Electro-communications under the Project. The focus is on the distance education and training via ETS-V overcoming the geographical extent and the cultural diversity of the Asia-Pacific Region.

This paper describes the architecture and simulated performance of a proposed Integrated Memory Array Processor (IMAP). The IMAP is an LSI which integrates a large capacity memory and a one dimensional SIMD processor array on a single chip. The IMAP holds, in its on-chip memory, data which at the same time can be processed using a one dimensional SIMD processor integrated on the same chip. All processors can access their individual parts of memory columns at the same time. Thus, it has very high processor-memory data transfer bandwidth, and has no memory access bottleneck. Data stored in the memory can be accessed from outside of the IMAP via a conventional memory interface same as a VRAM. Since the SIMD processors on the IMAP are configured in a one dimensional array, multiple IMAPs could easily be connected in series to create a larger processor and memory configuration. To estimate the performance of such an IMAP, a system architecture and instruction set were first defined, and on the basis of those two, a simulator and an assembly language were then developed. In this paper, simulation results are presented which indicate the performance of an IMAP in both image processing and artificial neural network calculations.

We observed a ship as a radar target embedded in sea clutter using a millimeter wave radar. The shape of the ship and sea clutter were discriminated by using texture analysis in image processing. As a discriminator, a nonlinear transformation of a local pattern was defined to deal with high order statistics.

A shift down of the resonance frequency is claimed to be used as a simple practical test for the onset of chaos based on a common feature of forced damped nonlinear oscillation systems which exhibit cascading bifurcations to chaos.

The authors examined the effect of feedbacking information on learners of their test results obtained through computerized tests. The learner's acceptability of computerized tests was revealed to be improved by distribution and explanation of newly devised feedback charts including data on one's response history and response latency during computerized testing that was carried out in formative evaluation. The feedback chart composed of graphic representation of relationship between degree of difficulty of each question and its response latency got a particularly high evaluation among learners. It was revealed that types of feedback chart that stood highest in learner's estimate varied with the learner traits. This observation will serve to develop educational systems that incorporate computerized tests into school lessons.

This paper describes a new method for the concurrent detection of faults in instruction level parallel (ILP) processors. This method uses the No OPeration (NOP) instruction slots that under branches, resource conflicts and some kind of data dependencies fill some of the pipelines (stages) in an ILP processor. NOPs are replaced by the copy of an effective instruction running in another pipeline. This allows the checking of the pipelines running the original instruction and its copy (ies), by the comparison of the outputs of their stages during the execution of the replicated instruction. We show some figures obtained for the application of this method to a two-pipeline superscalar processor.

Three dimensional (3-D) optics offers potential advantages to the massively-parallel systems over electronics from the view point of information transfer. The purpose of this paper is to survey some aspects of the 3-D optical interconnection technology for the future massively-parallel computing systems. At first, the state-of-art of the current optoelectronic array devices to build the interconnection networks are described, with emphasis on those based on the semiconductor technology. Next, the principles, basic architectures, several examples of the 3-D optical interconnection systems in neural networks and multiprocessor systems are described. Finally, the issues that are needed to be solved for putting such technology into practical use are summarized.

In this letter, we study on the sensitivity to the electrical stimulus pulse for biomedical electronics for the purpose to make a tactile vision substitution system for binds. We derive the equivalent circuit of finger by measuring sensitive voltages with various touch condition and various DC voltage. And we consider to the sensitivity of finger against electrical stimulus pulse. In order to convert the sense of sight to tactile sense, we consider four types of touch condition and various types of pulse. It is shown that the sensitivity of finger to electrical stimulus pulse is determined by duty-ratio, frequency, hight of pulse and the type of touch condition. In the case that duty-ratio is about 20%, frequency is within about 60-300Hz and touch condition is A-4 type, the sensitive voltage becomes the lowest. With this result, a tactile vision substitution system can be developed and the system will be used to transfer various infomations to blinds without paper.

A fuzzy inference processor which performs fuzzy inference with 12-bit resolution input at 200 kFLIPS (Fuzzy Logical Inference Per Second) has been developed. To keep the cost performance, not parallel processing hardware but processor type hardware is employed. Dedicated membership function generators, rule instructions and modified add/divide algorithm are adopted to attain the performance. The membership function generators calculate a membership function value in less than a half clock cycle. Rule instructions calculate the grade of a rule by one instruction. Antecedent processing and consequent processing are pipelined by the modified add/divide algorithm. As a result, total inference time is significantly reduced. For example, in the case of typical inference (about 20 rules with 2 to 4 inputs and 1 output), the total inference needs approximately 100 clock cycles. Furthermore by adding a mechanism to calculate the variance and maximum grade of the final membership function, it is enabled to evaluate the inference reliability. The chip, fabricated by 1 µm CMOS technology, contains 86k transistors in a 7.56.7 mm die size. The chip operates at more than 20 MHz clock frequency at 5 V.

Design of high-speed digital circuits such as adders and multipliers is one of the most important issues to implement high performance VLSI systems. This paper proposes a new multiple-valued code assignment algorithm to implement locally computable combinational circuits for k-ary operations. By the decomposition of a given k-ary operation into unary operations, a code assignment algorithm for k-ary operations is developed. Partition theory usually used in the design of sequential circuits is effectively employed for optimal code assignment. Some examples are shown to demonstrate the usefulness of the proposed algorithm.

To realize next-generation high performance ULSI processors, it is a very important issue to reduce the critical delay path which is determined by a cascade chain of basic gates. To design highly parallel digital operation circuits such as an adder and a multiplier, it is difficult to find the optimal code assignment in the non-linear digital system. On the other hand, the use of the linear concept in the digital system seems to be very attractive because analytical methods can be utilized. To meet the requirement, we propose a new design method of highly parallel linear digital circuits for unary operations using the concept of a cycle and a tree. In the linear digital circuit design, the analytical method can be developed using a representation matrix, so that the search procedure for optimal locally computable circuits becomes very simple. The evaluations demonstrate the usefulness of the circuit design algorithm.

This paper proposes new architecture LSIs based on wave-parallel computing to provide an essential solution to the interconnection problems in massively parallel processing. The basic concept is ferquency multiplexing of digital information, which enables us to utilize the parallelism of electrical (or optical) waves for parallel processing. This wave-parallel computing concept is capable of performing several independent binary funtions in parallel with a single module. In this paper, we discuss the design of wave-parallel image processing LSI to demonstrate the feasibility of reducing the number of interconnections among modules.

This paper's main objective is to analyze several procedures which select the model g among a set G of stochastic models to minimize the value of an information criterion in the form of L(g)H[g](zn)+(k(g)/2)c(n), where zn is the n observed data emitted by an information source θ which consists of the model gθ∈G and k(gθ) mutually independent stochastic parameters in the model gθ∈G, H[g](zn) is (-1) (the maximum log likelihood value of the data zn with respect to a model g∈G), and c(n) is a predetermined function (penalty function) of n which controls the amount of penalty for increasing the model size. The result is focused on specific performances when the information criteria are applied to the framework of so-called state decomposition. Especially, upper bounds are derived of the following two performance measures for each penalty function c(n): the error probability of the model selection, and the average Kullback-Leibler information between the true information source and the estimated information source.

In this paper we discuss a neural network model that can recognize patterns rotated at various angles. The model employs copy learning, a learning method entirely different from those used in conventional models. Copy-Learning is an effective learning method to attain the desired objective in a short period of time by making a copy of the result of basic learning through the application of certain rules. Our model using this method is capable of recognizing patterns rotated at various angles without requiring mathematical preprocessing. It involves two processes: first, it learns only the standard patterns by using part of the network. Then, it copies the result of the learning to the unused part of the network and thereby recognizes unknown input patterns by using all parts of the network. The model has merits over the conventional models in that it substantially reduces the time required for learning and recognition and can also recognize the rotation angle of the input pattern.

Based on distributed artificial intelligence technology, the paper proposes a distributed expert system for distribution system planning. The developed expert system is made up of a set of problem-solving agents that autonomously process local tasks and cooperatively interoperate with each other by a shared database in order to reach a proper distribution plan. In addition, a two-level control mechanism composed of local-control and meta-control is also proposed to achieve a high degree of goodness in distribution system planning. To demonstrate its effect, the distributed expert system is implemented on basis of NASA's CLIPS and SUN's RPC and applied to the planning of distribution system in Taiwan. Test results indicate that the distributed expert system assists system planners in making an appropriate plan.

In this paper, we show that without any unproven assumption, there exists a "four" move blackbox simulation perfect zero-knowledge interactive proof system of computational ability for any random self-reducible relation R whose domain is in BPP, and that without any unproven assumption, there exists a "four" move blackbox simulation perfect zero-knowledge interactive proof system of knowledge on the prime factorization. These results are optimal in the light of the round complexity, because it is shown that if a relation R has a three move blackbox simulation (perfect) zero-knowledge interactive proof system of computational ability (or of knowledge), then there exists a probabilistic polynomial time algorithm that on input x ∈ {0, 1}*, outputs y such that (x, y)∈R with overwhelming probability if x ∈dom R, and outputs "⊥" with probability 1 if x dom R.

This paper's main objective is to clearly describe the construction of a universal code for minimizing Davisson's minimax redundancy in a range where the true model and stochastic parameters are unknown. Minimax redundancy is defined as the maximum difference between the expected persymbol code length and the per-symbol source entropy in the source range. A universal coding scheme is here formulated in terms of the weight function, i.e., a method is presented for determining a weight function which minimizes the minimax redundancy even when the true model is unknown. It is subsequently shown that the minimax redundancy achieved through the presented coding method is upper-bounded by the minimax redundancy of Rissanen's semi-predictive coding method.

This letter describes the High-speed Statistical Retry switch (HSR switch) for high-speed ATM switching systems. The HSR switch uses a new matrix-shaped switching structure with buffers at input and ouptut ports, and a simple retry algorithm. The input buffers are very small, and no complicated arbitration function is employed. A cell is repeatedly transmitted from each input buffer at m times the input line speed until the input buffer receives an acknowledge signal from the intended output buffer. A maximum of one cell can be transmitted from each input buffer during the cell transmission time. The internal ratio (m) is decided according to the probability of cell conflict in the output line. Simulation results show that just a 10-cell buffer at each input port and a 50-cell buffer at each output port are required when m=4 to achieve a cell loss probability of better than 10-8, irrespective of the switch size. At each crosspoint, cells on the horizontal input line take precedence over those on the vertical input line. Only a very simple retry algorithm is employed, no complex arbitration is needed, and the arbitration circuit at the crosspoint can be reduced by about 90% in size. The proposed ATM switch architecture is applicable to high-speed (Gbit/s) ATM switches for B-ISDN because of its simplicity.

An automatic tap assignment method in sub-band adaptive filter is proposed in this letter. The number of taps of the adaptive filter in each band is controlled by the mean-squared error. The numbers of taps increase in the bands which have large errors, while they decrease in the bands having small errors, until residual errors in all the bands become the same. In this way, the number of taps in a band is roughly proportional to the length of the impulse response of the unknown system in this band. The convergence rate and the residual error are improved, in comparison with existing uniform tap assignment. Effectiveness of the proposed method has been confirmed through computer simulation.