In a two-layer self-diplexing antenna fed at two ports, theoretical analysis has already shown that the isolation characteristics can be improved by adjusting the angle between the feed locations of the transmitting and receiving antennas. In this letter, we experimentally investigate the isolation characteristics of the self-diplexing array antenna. First, calculated and experimental results for each feed location of the element antenna are compared and good agreement is found. Second, experimental results with a 19-element planar array indicate that a self-diplexing antenna with suitably chosen feed configuration is effective in improving the isolation in a phased array antenna.

This paper describes the learning performance of the deterministic Boltzmann machine (DBM), which is a promising neural network model suitable for analog LSI implementation. (i) A new learning procedure suitable for LSI implementation is proposed. This is fully-on-line learning in which different sample patterns are presented in consecutive clamped and free phases and the weights are modified in each phase. This procedure is implemented without extra memories for learning operation, and reduces the chip area and power consumption for learning by 50 percent. (ii) Learning in a layer-type DBM with one output unit has characteristic local minima which reduce the effective number of available hidden units. Effective methods to avoid reaching these local minima are proposed. (iii) Although DBM learning is not suitable for mapping problems with analog target values, it is useful for analog data discrimination problems.

A speech coding scheme at 3.6 kbit/s has been proposed. The scheme is based on CELP (Code Excited Linear Prediction) with pitch synchronous innovation, which means even random codevectors as well as adaptive codevectors have pitch periodicity. The quality is comparable to 6.7 kbit/s VSELP coder for the Japanese cellular radio standard.

This system called COKIS automatically extracts knowledge about C functions from the UNIX on-line manual by using its description paragraph and the user can interactively inquire to the system in order to know about UNIX C functions. The idea is motivated on the one side to free users from being involved in an exhaustive knowledge acquisition in the past, and to examine problems in understanding knowledge itself on the other. We propose Memory Processor which is implemented to realize extracting knowledges from corpus and processing dialogues in the inquiry system at the same modules.

We propose a fully digital architecture for Kohonen network suitable for VLSI implementation. The proposed architecture adopts a functional memory type parallel processor (FMPP) architecture which has a structure similar to a content addressable memory (CAM). One word of CAM is regarded as a processing element and a group of elements forms a neuron. All processing elements execute the same operation in bit-serial but in processor-parallel. Thus the number of instructions for realizing the network algorithm is independent of the number of neurons in the network. With reference to a previously reported CAM, we estimate a network with 96 neurons for speech recognition could be integrated on three chips using a 1.2 µm process, and it operates 50 times faster than a sequential hardware. Owing to its highly regular structure of memories, the proposed hardware architecture is well compatible with current VLSI technology.

A new neural network system for object recognition is proposed which is invariant to translation, scaling and rotation. The system consists of two parts. The first is a preprocessor which obtains projection from the input image plane such that the projection features are translation and scale invariant, and then adopts the Rapid Transform which makes the transformed outputs rotation invariant. The second part is a neural net classifier which receives the outputs of preprocessing part as the input signals. The most attractive feature of this system is that, by using only a simple shift invariant transformation (Rapid transformation) in conjunction with the projection of the input image plane, invariancy is achieved and the system is of reasonably small size. Experiments with six geometrical objects with different degrees of scaling and rotation shows that the proposed system performs excellent when the neural net classifier is trained by the Cascade-correlation learning algorithm proposed by Fahlman and Lebiere.

We propose a new architecture of Functional Memory type Parallel Processor (FMPP) architectures called bit-parallel block-parallel (BPBP) FMPP. Design details of a prototype BPBP FMPP chip are also shown. FMPP is a massively parallel processor architecture that has a memory-based simple two-dimensional regular array structure suitable for memory VLSI technology. Computation space increases as integration density of memory increases. Computation time does not depend on the number of processors. So far, a bit-serial word-parallel (BSWP) implementation based on a content addressable memory (CAM) is mainly investigated as one of promising architectures of FMPP. In a BSWP FMPP, each word of a CAM works as a processor, and the amount of hardware is minimized by abopting a bit-serial operation, thus maximizing integration scale. The BSWP FMPP, however, does not allow operations between two words, which restriction limits the applicability of the BSWP FMPP. On the other hand, the proposed BPBP FMPP is designed to execute logical and arithmetic operations on two words. These operations are performed simultaneously on every group of words called a block. BPBP FMPP hereby achieves a high performance while maintaining high integration density of the BSWP, and is suitable for various applications.

Since semiconductor memory chip has been growing rapidly in its capacity, memory testing has become a crucial problem in RAMs. This paper proposes a new RAM test algorithm, called generalized marching test (GMT), which detects static and dynamic pattern sensitive faults (PSF) in RAM chips. The memory array with N cells is partitioned into B sets in which every two cells has a cell-distance of at least d. The proposed GMT performs the ordinary marching test in each set and finally detects PSF having cell-distance d. By changing the number of partitions B, the GMT includes the ordinary marching test for B1 and the walking test for BN. This paper demonstrates the practical GMT with B2, capable of detecting PSF, as well as other faults, such as cell stuck-at faults, coupling faults, and decoder faults with a short testing time.

To speed up a guided-probe diagnosis process, the number of probed lines needs to be reduced. This paper presents two efficient probing line determination methods by which the number of probed lines is either small or minimum. The concept of fault probability is introduced to reflect the fact that not all gates have the same probability to be faulty. Experimental results show the effectiveness of the proposed methods.

This paper proposes a multi-layer cellular network in which a self-organizing method is implemented. The network is developed for the purpose of data clustering and recognition. A multi-layer structure is presented to realize the sophisticated combination of several sub-spaces which are spanned by given input characteristic data. A self-organizing method is useful for evaluating the set of clusters for input data without a supervisor. Thus, using these techniques this network can provide good clustering ability as an example for image/pattern data which have complicated and structured characteristics. In addition to the development of this algorithm, this paper also presents a parallel VLSI architecture for realizing the mechanism with high efficiency. Since the locality can be kept among all processing elements on every layer, the system is easily designed without large global data communication.

In order to describe the flow passing through the glottis, we constructed a dynamic three-dimensional finite element model of the human larynx. The transient flow fields in the laryngeal model were calculated to examine the dynamic effects generated by the vocal fold vibration. A phase difference between the upper and lower edges of the vocal folds was included in the model to investigate the effect of the glottal shapes on pressure-flow relationships in the larynx during the vocal fold vibration. Using STAR-CD thermofluids analysis system, which is capable of treating the transient flow in moving-boundary situations with finite volume method, we solved the viscous incompressible Navier-Stokes equations to investigate the glottal flows and transglottal pressures as a function of the vocal fold vibration. The results were compared to the uniform glottis model and the theoretical model proposed by Ishizaka and Matsudaira, respectively. The effects of dynamic factors on the pressure distributions and flow patterns in the larynx resulting from the vocal-fold vibration were also discussed.

A new type jacket cutter for optical fibers is designed, and it is confirmed experimentally that its performance is superior to those of the conventional cutters. Using this new cutter which is mainly consisted of a rotatable fiber holder and a pair of blades separated by a distance of 0.3-0.4mm, only the tight jacket is cut and removed while the primary coating and the fiber are kept intact. As the result, the probability of damage to the fiber surface during jacket removal is reduced to about 0% compared to 10% found in the case of a conventional cutter. This result is useful to increase the reliability of optical fibers during assembling efforts.

The singular point analysis, such as the Painlev test and Yoshida's test, is a computational method and has been implemented in a symbolic computational manner. But, in applying the singular point analysis to high dimensional and/or "complex" dynamical systems, we face with some computational difficulties. To cope with these difficulties, we propose a new numerical technique of the singular point analysis with the aid of the self-validating numerics. Using this technique, the singular point analysis can now be applicable to a wide class of high dimensional and/or "complex" dynamical systems, and in many cases dynamical properties such as the algebraic non-integrability can be proven for such systems.

The locally exhaustive testing of multiple output combinational circuits is the test which provides exhaustive test patterns for each set of inputs on which each output depends. First, this paper presents a sufficient condition under which a minimum test set (MLTS) for the locally exhaustive testing has 2w test patterns, where w is the maximum number of inputs on which any output depends. Next, we clarify that any CUT with up to four outputs satisfies the condition, independently of w and n, where n is the number of inputs of the CUT. Finally, we clarify that any CUT with five outputs also satisfies the condition for 1w2 or n2wn.

The authors developed new measuring system (Holographic Pattern Measuring System [HPMS]), which is composed of both techniques of holography and graphic image processing, was used to measure the vibrations of a printed circuit board (PCB) due to operation of a mounted electromagnetic relay on it. The clear vibration patterns were obtained. By using pattern analysis processor, quantitative vibration patterns of the PCB surface were observed. Both the vibration patterns and displacements were changed by edge fixing way of the PCB.

A new transfer mode and a switching architecture which can support loss free and no delay jitter service class with shorter switching delay compared with "stop and go queueing scheme" is proposed. This scheme combines ATM scheme with hierarchical STM framing concept.

An estimation method of region is presented, in which a solution path of the so-called Newton type homotopy equation in guaranteed to exist, it is applied to a certain class of uniquely solvable nonlinear equations. The region can be estimated a posteriori, and its upper bound also can be estimated a priori.

A laser system which has a mirror outside of it to feedback a delayed output has been described by the Maxwell-Bloch equations with time delay. It is shown that a chaotic behavior in the equations can be controlled by using a OPF control algorithm. Our numerical simulation indicates that the chaotic behavior is stabilized on 1, 2 periodic unstable orbits.

Intermittent chaos was observed in the silicon thyristor circuit without external elements of L and C, under the condition of ac excitation at the anode. Lorenz plot reconstructed from the experimental waveform and the numerical simulation of this kind of intermittency fairly agreed with each other.

The advantages of a neuro-chip architecture based on a DRAM are demonstrated through a discussion of the general issuse regarding a memory based neuro-chip architecture and a comparison with a chip based on an SRAM. The performance of both chips is compared assuming digital operation, a 1.5-V supply voltage, a 106-synapse neural network capability, and a 0.5-µm CMOS design rule. The use of a one-transistor DRAM cell array for the storage of synapse weights results in a chip 55% smaller than an SRAM based chip with the same 8-Mbit memory capacity and the same number of processing elements. No additional operations for refreshing the DRAM cell array are necessary during the processing of the neural networks. This is because all the synapse weights in the array are transferred to the processing elements during the processing and the DRAM cells in the array are automatically refreshed when they are selected. The precharge operation of the DRAM cell array degrades the processing speed, however a processing speed of 1.37 GCPS is expected for the DRAM based chip. That speed is comparable to the 1.71 GCPS for the SRAM based chip with the same 256 parallel-processing elements. A DRAM cell array has the additional advantage of lower power dissipation in this specific usage for the neuro-chip. The dynamic operation of the DRAM cell array results in a 10% lower operating power dissipation than a chip using an SRAM cell array at the same processing speed of 1.37 GCPS. That lower operating power dissipation enables a DRAM based chip to run on a 1.5-V dry cell for longer under intermittent daily use even though the SRAM cell array has little power dissipation in data-holding mode.