This letter investigates sidelobe levels of a two-bit digital phased array composed of a small number of elements. Among several phase shifter designs applicable to phased arrays, a two-bit design needs the least number of circuit elements so that the development and manufacturing need the lowest cost. Now the following questions arise. Is a two-bit phased array practical? How low can its sidelobe level be reduced? To answer the questions, three methods are tried to reduce the sidelobe level of a uniformly-excited linear array of isotropic elements. The methods are the quadratic-phase feed method, the partially randomizing method of periodic phase errors, and the genetic algorithm (GA) approach. Among the methods, the quadratic-phase feed method provides the lowest sidelobe level around -12.5 dB - -13.2 dB in the steering angles from 0 to 48 degrees for a 21-element, half-wavelength spacing array, and -11.2 dB - -13.0 dB in the steering angles from 0 to 30 degrees for an 11-element, 0.6-wavelength spacing array. Although it depends on the system requirement, these values would be acceptable in some applications, hence a two-bit phased array designed properly may be practical in an actual system.

We have studied an image acquisition system for a real-time image- based rendering (IBR) system. In this area, most conventional systems sacrifice spatial or temporal resolution for a large number of input images. However, only a portion of the image data is needed for rendering, and the portion required is determined by the position of the imaginary viewpoint. In this paper, we propose an acquisition system for a real-time image-based rendering system that uses pixel-based random-access image sensors to eliminate the main bottleneck in conventional systems. We have developed a prototype CMOS image sensor, which has 128 128 pixels. We verified the prototype chip's selective readout function. We also verified the sample & hold feature.

As a center of mobile multimedia of the 21st century, it is very much looking forward to explosion of R&D and business of the next generation of mobile communication systems and the ITS (Intelligent Transport Systems) because ITS will enable information-oriented in the field of the road, traffic and vehicles, by using the most advanced technologies of mobile communications and devices, for the various purposes such as decrease of the traffic accident, the reduction of traffic jam, the increase in efficiency of the logistics and the harmony with the earth environment. This invited paper will first briefly introduce evolution of mobile communications and ITS in ministries, industries and academia in Japan. Then core communication technologies for ITS will be overviewed such as spread spectrum CDMA, adaptive antenna array, and software radio or software defined radio. Demands of SoC (System on a Chip) to carry out the core technologies will be addressed.

A method for fast calibration of digital-beam-forming (DBF) receiving array antennas by means of digital signal processing is described. It uses plane wave arriving from a known direction that contains a known reference sequence. Non-uniformities of the amplitude and phase in the branches are detected and calibrated in real time by the complex correlation of a replica of the known reference sequence with the received signal obtained from the output signals of each element. No special circuit for calibration is required, and the non-uniformities can quickly be compensated for by digital signal processing even for an array antenna with many antenna elements. This method enables highly accurate calibration of large-scale array antennas operating at a high frequency even under a low signal-to-noise power ratio (SNR).

A robust adaptive beamforming method is proposed to cancel coherent, as well as incoherent, interference using an array of arbitrary geometry. In this method, coherent interferences are suppressed by a transformation of received data with the estimates of their arrival angles and then, to reject incoherent interferences, the array output power is minimized subject to the look direction constraint in the transformed signal-plus-interference (TSI) subspace. This TSI subspace-based beamforming results in robustness to errors in the angle estimations. Its performance is theoretically examined. The theoretic results conform to simulation results. It is straightforward to apply the theoretic results to the performance analysis of subspace-based adaptive beamfomers only for incoherent interference cancellation.

Eigenstructure-based beamformers suffer form performance degradation due to pointing errors when the number of the incident signals is incorrectly detected or when the desired signal is much stronger than the interferences. We present a robust beamformer with the self-correction of look direction errors, based on the Newton method. Even though there are errors in the detection of the incident signal number as well as in the presumed look direction, it can achieve optimum performance with no errors.

In this paper, we propose a method of unicast and broadcast packet sharing for the orthogonal frequency division multiplexing (OFDM) multi-base station (BS) indoor wireless communication system using an adaptive array antenna on mobile terminals. The adaptive array antenna placed on the mobile terminal allows quality improvement due to the diversity effect when the data transmitted from all BSs are the same, and provides capacity improvement by channel sharing when the data from each BS are different. In the proposed sharing method, unicast packets are transmitted independently from multiple BSs in order to increase the communication capacity, and broadcast packets are transmitted simultaneously with other BSs in order to enhance the communication quality without retransmission. Furthermore, by modifying the packet assignment procedure, we confirm that quality can be improved for unicast packets in a low traffic environment.

We give an overview of the computational complexity of linear and mesh-connected cellular and iterative arrays with respect to well known models of sequential and parallel computation. We discuss one-way communication versus two-way communication, serial input versus parallel input, and space-efficient simulations. In particular, we look at the parallel complexity of cellular arrays in terms of the PRAM theory and its implications, e.g., to the parallel complexity of recurrence equations and loops. We also point out some important and fundamental open problems that remain unresolved. Next, we investigate the solvability of some reachability and safety problems concerning machines operating in parallel and cite some possible applications. Finally, we briefly discuss the complexity of the "commutativity analysis" technique that is used in the areas of parallel computing and parallelizing compilers.

Technique of Measuring 3-D velocity vector components is important for the correct diagnosis of the blood flow pattern and quantitative assessment of intratumor perfusion. However, present equipment based on ultrasonic Doppler can not provide us true 3-D velocity. To overcome the problem, we previously proposed a new method of 3-D velocity vector measurement. The method uses 2-D array probe and enable us to obtain three components of velocity vector with real time by integrating the Doppler phase shift on the each element with the relative small single aperture compared with conventional method. Basic performance of the method has been evaluated by computer simulation. In this paper, to evaluate the feasibility of the proposed method, experimental investigation using a simple ring array probe and a phantom were carried out. Three components of velocity vector for different velocity magnitude and flow direction were measured. Experimental results validated its ability of measuring 3-D velocity and its feasibility.

Low-crosstalk 1.3-µm Fabry-Perot laser diode (FP-LD) and photodiode (PD) arrays are developed. The arrays are fabricated on semi-insulating substrates and their anodes and cathodes are separated channel by channel to suppress inter-channel electrical crosstalk at high frequency. Crosstalk of less than -30 dB is achieved between neighboring LDs at 3.125 GHz. This is low enough for BER characteristics observed under asynchronous operation of a 4-channel LD array to be no worse than those under single-channel operation. Excellent uniformity of both LD and PD characteristics, high-temperature operation of the LD array, and low-voltage operation of the PD array are also attained. These arrays are suitable for low-cost high-bit-rate parallel optical communications.

It is well known that interpath interference (IPI) is a major factor that limits the performance of high data rate transmissions over a variable spreading factor wideband-CDMA (W-CDMA) link since the spreading factor is in general small. An optimum combining scheme suppressing IPI was recently proposed for RAKE reception in [1]. The main contribution of this letter is to present a theoretical model for the outage probability and bit error probability of a RAKE receiver utilizing the optimum combining scheme. Analytical and simulation results are closely matched and show that the optimum scheme provides significant performance improvement compared to the conventional maximum ratio combining (MRC) scheme.

This paper treats the data routing problem for fault-tolerant systolic arrays based on Triple Modular Redundancy (TMR) in mixed spatial-temporal domain. The number of logical links required in TMR systolic array is basically 9 times larger than the one for corresponding non-fault-tolerant systolic array. The link sharing is a promising method for reducing the number of physical links, which may, however, degrade the fault tolerance of TMR system. This paper proposes several robust data-routing and resource-sharing (plural data transfers share a physical link, or a data transfer and a computational task share a PE as a relay node for the former and as a processor for the latter), by which certain classes of fault tolerant property will be guaranteed. A stage and a dominated set are introduced to characterize the features of routing/resource-sharing in TMR systems, and conditions on the dominated set and their resultant fault-tolerant properties are derived.

We analyzed the performance of adaptive array antennas with a RAKE receiver by employing a common correlation matrix of the sample matrix inversion (CCM-SMI) algorithm in a multipath Rayleigh fading environment for W-CDMA reverse link. A common correlation matrix is usually used to provide adaptive weights for multiple users and multiple delay paths and can be used in packet communications transmitted using frame units. The proposed CCM-SMI algorithm had a better BER and SINR for lower computational complexity compared with the conventional SMI algorithm, even when using a RAKE receiver in multipath Rayleigh fading environment.

A micro reactor array for biochemical or biomedical use was developed. Conceptof this development is to get as much as biological data at the same time. Ninety-six micro reaction wells, volume of each well was 1.5 µl, were integrated in the array. The micro reactor array was fabricated on 1 mm thick silicon wafer and twelve pairs of a temperature sensor and a heater were formed on the backside. A tiny transparent window for optical measurement was formed at the center of bottom wall on each well. Several temperature gradients were applied to the array by means of few heaters and compared with simulation results to optimize the parameters. Finally, performance of the array was evaluated by basic DNA reaction. Advantages of the array system are the fast thermal response due to the small heat capacity and easy to make several reaction conditions in parallel.

This paper investigates the optimum transmit-antenna-weight generation method for adaptive antenna array transmit diversity (AAA-TD) in the W-CDMA forward link: AAA-TD with beam and null steering (BNST), AAA-TD with beam steering (BST), or switched beam transmit diversity with fixed weights (SBTD-FW). The achievable BER performance after carrier frequency calibration in the transmit beam pattern is compared among the three methods assuming a different carrier frequency in a 2-GHz band with the carrier separation of 184.5 MHz based on computer simulations. The simulation results show that the achievable BER performance in the forward link using AAA-TD with BNST is almost identical to that using AAA-TD with BST when there are many more interfering users than there are array antennas, except for the special case when a small number of higher rate users exists in the reverse link. This is because by performing carrier frequency calibration, the directions of the beam nulls are shifted from the real directions of arrival (DOAs) of the interfering users. However, we also show that the required transmit Eb/N0 at the average BER of 10-3 using AAA-TD with BST is decreased by approximately 1.0 to 1.2 dB compared to that using SBTD-FW with 12 beams.

A mesh-connected processor array consists of many similar processing elements (PEs), which can be executed in both parallel and pipeline processing. For the implementation of an array of large numbers of processors, it is necessary to consider some fault tolerant issues to enhance the (fabrication-time) yield and the (run-time) reliability. In this paper, we introduce the 1(1/2)-track switch torus array by changing the connections in 1(1/2)-track switch mesh array, and we apply our approximate reconfiguration algorithm to the torus array. We describe the reconfiguration strategy for the 1(1/2)-track switch torus array and its realization using WSI, especially 3-dimensional realization. A hardware realization of the algorithm is proposed and simulation results about the array reliability are shown. These imply that a self-reconfigurable system with no host computer can be realized using our method, hence our method is effective in enhancing the run-time reliability as well as the fabrication-time yield of processor arrays.

This paper presents a CAD technology mapping algorithm for LUT-based FPGAs. Since interconnections in an FPGA must be accomplished with limited routing resources, routability is the most important objective in a technology mapping algorithm. To optimize routability, the goal of the algorithm is the production of a design with a minimum interconnection. The Min-cut algorithm is first used to partition a graph representing a Boolean network into clusters so that the total number of interconnections between clusters is minimum. To decrease further the number of interconnections needed, clusters are then merged into larger clusters by a pairing technique. This algorithm has been tested on the MCNC benchmark circuits. Compared with other LUT-based FPGA mapping algorithms, the algorithm produces better routability characteristics.

First, we give a graph-theoretic formalization for the spare assignment problems for two cases of reconfiguring NN mesh-connected processor arrays with spares on a diagonal line in the array or two orthogonal lines at the edges of the array. Second, we discuss the problems for minimizing the numbers of "dangerous processors" for the cases. Here, a dangerous processor is a nonfaulty one for which there remains no spare processor to be assigned if it becomes faulty, without modifying the spare assignments to other faulty processors. The problem for the latter case, originally presented by Melhem, has already been discussed and solved by the O(N2) algorithm in [3], but it's procedure is very complicated. Using the above graph-theoretic formalization, we give efficient plain algorithms for minimizing the numbers of dangerous processors by which the problems for both the cases can be solved in O(N) time.

We examine diagnosis of processor array systems formed as two-dimensional grids, with boundaries, and either four or eight neighbors for each interior processor. We employ a parallel test schedule. Neighboring processors test each other and report the results. Our diagnostic objective is to find a fault-free processor or set of processors. The system may then be sequentially diagnosed by repairing those processors tested faulty according to the identified fault-free set. We establish an upper bound on the maximum number of faults that can be sustained without invalidating the test results under worst case conditions. We give test schedules and diagnostic algorithms that meet the upper bound as far as the highest order term. We compare these near optimal diagnostic algorithms to alternative algorithms--both new and already in the literature.

This paper presents a new framework for synthesizing look-up table (LUT) networks. Some of the existing LUT network synthesis methods are based on one or two functional (Boolean) decompositions. Our method also uses functional decompositions, but we try to use various decomposition methods, which include algebraic decompositions. Therefore, this method can be thought of as a general framework for synthesizing LUT networks by integrating various decomposition methods. We use a cost database file which is a unique characteristic in our method. We also present comparisons between our method and some well-known LUT network synthesis methods, and evaluate the final results after placement and routing. Although our method is rather heuristic in nature, the experimental results are encouraging.