This paper describes a 0.35µm SOI-CMOS gate array using partially-depleted transistors. The gate array adopts the field-shield isolation technique with body-tied structures to suppress floating-body problems such as: (1) kink characteristics in drain currents, (2) low break-down voltage, and (3) frequency-dependent delay time. By optimizing the basic-cell layout and power-line wiring, the SOI-CMOS gate array also allows the use of the cell libraries and the design methodologies compatible with bulk-CMOS gate arrays. An ATM (Asynchronous Transfer Mode) physical-layer processing LSI was fabricated using a 0.35µm SOI-CMOS gate array with 560k raw gates. The LSI operated at 156 Mbps at 2.0 V, while consuming 71% less power than using a typical 0.35µm 3.3 V bulk-CMOS gate array.

A novel algorithm for an adaptive array that is suitable for a multi-carrier transmission will be proposed in this paper. In an adaptive array, signals received by antenna elements are weighted and combined together. In the proposed algorithm, distortion of a spectrum of the combined signal is detected and weight coefficients for each antenna element are controlled so that the spectrum of the combined signal becomes flat. Concept of the proposed algorithm can be interpreted as the CMA which is applied to signals sampled in the frequency domain. Furthermore, a configuration of the adaptive array will be shown. Signals separated in a receiver of the multi-carrier transmission are utilized to detect the distortion of the signal spectrum. By adopting the proposed configuration, the spectrum of the multi-carrier signal can be easily detected. In order to investigate the performance of the proposed adaptive array, computer simulation has been carried out. Numerical results show that; 1) A desired wave is captured well even if an interference wave is narrow band signal and is stronger than the desired wave. 2) Suppression performance for a co-channel interference wave depends on both a symbol timing and SIR of arrival waves. If the symbol timing of the interference wave greatly differs from the timing of FFT window of the receiver, the desired wave can be captured even if the co-channel interference wave is stronger more than 10 dB compared with the desired wave. The conventional CMA adaptive array has a serious problem that the narrow band interference wave is captured when it is stronger than the desired wave. On the other hand, it is extremely rare that the proposed adaptive array captures the narrow band interference wave. Therefore, it can be said that the proposed adaptive array is a robust system compared with the conventional system.

In phased array antennas, the number of radiator rows is one of the important factors to minimizing both cost and weight. Therefore, the antenna tilt angles having relation with the element spacing are among the important design parameters. In this paper, the optimum tilt angles for several types of dipole planar arrays are investigated theoretically. To obtain optimum tilt angles, the directivity equation including phase shift factors for planar arrays are calculated.

The genetic algorithm is used to synthesize the directional circular arc array as a sectored antenna. Then, the performance of this sectored antenna in indoor wireless millimeter wave channel is investigated. Based on the desired pattern and the topography of the antennas, the synthesis problem can be reformulated into an optimization problem and solved by the genetic algorithm. The genetic algorithm will always converge to global extreme instead of local extreme and achieves a good approximation to the desired pattern. Next, the impulse responses of the indoor channel for any transmitter-receiver location are computed by shooting and bouncing ray/image techniques. By using the impulse response of multipath channel, the performance of the sectored antenna on BPSK (binary phase shift keying) system with phase and timing recovery circuits is presented. Numerical results show that the synthesized sectored antenna is effective to combat the multipath fading and can increase the transmission rate of indoor millimeter wave system.

It is the purpose of this paper to review the generation of quantized voltage steps in Josephson-junctions, and also the recent practical application of these precise measurements. A 10-V Josephson-junction-array-voltage standard system has been established with a Josephson-junction-array, a phase-locked millimeter wave, and a precise null-detection system. Based on these technologies, the AC Josephson effect has been applied to other precise measurements such as DC error voltage of a multi-integrating analog-to-digital converter and for a pulse-width-modulation type precise voltage calibrator.

The MC-CDMA (multi-carrier code division multiple access) technique is known to be appropriate for high data-rate wireless communications such as mobile multimedia communication due to its robustness to multipath fading and its capability of handling high data rates with a simple one-tap equalizer. In this paper, the performance of an MC-CDMA system employing antenna array at the base station in a fading channel is presented. Following the discussion of optimal beamformer not requiring explicit DOA (direction of arrival) or training signals, it is shown that the interference from other users within a cell can be significantly reduced for both reverse link (mobile to base station) and forward link (base station to mobile) using an MC-CDMA with antenna array, thus increasing the system's user-capacity. Computer simulations that demonstrate user-capacity improvement of the proposed approach are discussed.

The design of array processors for solving linear systems using two-step division-free Gaussian elimination method is considered. The two-step method can be used to improve the systems based on the one-step method in terms of numerical stability as well as the requirements for high-precision. In spite of the rather complicated computations needed at each iteration of the two-step method, we develop an innovative parallel algorithm whose data dependency graph meets the requirements for regularity and locality. Then we derive two-dimensional array processors by adopting a systematic approach to investigate the set of all admissible solutions and obtain the optimal array processors under linear time-space scheduling. The array processors is optimal in terms of the number of processing elements used.

We propose a model for fault tolerant 3D processor arrays using one-and-half track switches. Spare processors are laid on the two opposite surfaces of the 3D array. The fault compensation process is performed by shifting processors on a continuous straight line (called compensation path) from a faulty processor to a spare on the surfaces. It is not allowed that compensantion paths are in the near-miss relation each other. Then, switches with only 4 states are needed to preserve the 3D mesh topology after compensating for faults. We give an algorithm in a convenient form for reconfiguring by hardware the 3D mesh arrays with faults. The algorithm can reconfigure the 3D mesh arrays in polynomial time. By computer simulation, we show the survival rates and the reliabilities of arrays which express the efficiencies of reconfiguration according to the algorithm. The reliabilities are compared with those of the model using double tracks for which the near-miss relation among compensation paths is allowed, but whose hardware overhead is almost double of that of the proposed model using one-and-half track. Finally, we design a logical circuit for hardware realization of the algorithm. Using the circuit, we can construct such a built-in self-reconfigurable 3D mesh array that the reconfiguration is done very quickly without an aid of a host computer.

This paper discusses the employment of adaptive array antennas at the base station of a Multi Processing Gain (MPG) CDMA system. It is shown that the adaptive array antenna with the weight control scheme based on the signal before despreading procedure does not increase but even decreases the performance than that with an omni-directional antenna, and the cause of this serious performance degradation is revealed. Then it is shown that the performance with the weight control scheme based on the signal after despreading procedure is always better than that with an omni-directional antenna. Furthermore, the possibilities of performance improvement by the combination of adaptive array antenna and interference cancellation techniques are mentioned.

Recent attractive high-speed networks require network file servers with high-speed read performance to deliver huge multimedia files, like voice or movie files. This paper proposes new design and implementation techniques that yield high-speed file servers based on UNIX. The techniques are request reduction, in which contiguous blocks on UNIX file system (UFS) are gathered for reducing the number of command requests from the file system to the device driver, and a direct access method for cutting through the buffer cache mechanism. A file server prototype based on a general-purpose personal computer (PC) is constructed and its performance is evaluated. The preliminary results show that the prototype achieves high-speed file read performance in excess of 100 Mbytes/s even on an OpenBSD PC-UNIX system with 3 RAID controllers and 9 hard drives in RAID level 0 configuration.

Miniaturized opto and microwave receiver module using DCCPWs (Double Conductor Coplanar Waveguides) have been developed for active phased array antennas. The module comprised by a microstrip-to-slot transition, two chips of low-noise MMIC amplifiers, and a laser diode module is fabricated on an ultra-thin package with 10301.5 mm3 in size and 2 g in weight to achieve an ultra-thin structure of active phased array antenna panels. The ultra-thin structure is attributed to the design of low-noise MMIC amplifiers using DCCPWs and laser diode modules using silicon V-groove technology and fiber alignment method.

Due to the large number of I/O's in a Ball-Grid-Array (BGA) package, routing becomes more and more an important work. A ring-based router for the BGA package is presented in this paper to interconnect each I/O pad of a chip to a corresponding ball distributed on the substrate area. The major phases for the router consist of layer assignment, topological routing, and physical routing. Using this router, we can generate an even distribution of planar and any-angle wires to improve manufacturing yield. We have also conducted various testing examples to verify the efficiency of this router. Experiments show that the router produces very good results, far better than the manual design, thus it can be applied to the practical packaging of integrated circuits.

The constant modulus algorithm (CMA) of the adaptive array has been developed for suppressing the co-channel interference and the intersymbol interference in mobile communications. In this paper a novel CMA for the hybrid of the adaptive array and equalizer (HAE) is proposed to combat the problems of insufficient degrees of freedom and mainbeam multipath interferers. The HAE with CMA utilizes the constant modulus property for the output signal of the HAE to adjust the weight vectors of the array and equalizer simultaneously. The co-channel interferers can be canceled by the array and the multipath interferers can be removed by the array or the equalizer following the array in the HAE. Therefore, the array in the HAE with CMA may need less number of elements than that required by the CMA array which cancels both the co-channel interferers and multipath interferers. Besides, the presence of the mainbeam multipath interferers, which may seriously degrade the performance of the CMA array, has much less effect on the HAE with CMA since it can be suppressed by the equalizer instead of the array. Simulation results are presented to demonstrate the merits of the CMA for the HAE.

Systolic array implementations of modified Gaussian eliminations for the decoding of an (n, n-2t) RS code, including the Hong-Vetterli algorithm and the FIA proposed by Feng and Tzeng, are designed in this paper. These modified Gaussian eliminations are more easily understanding than the classical Berlekamp-Massey algorithm and, in addition, are efficient to decode RS codes for small e or e <

This paper presents unified VLSI architectures which can efficiently realize some widespread one-dimensional (1-D) and two-dimensional (2-D) real discrete trigonometric transforms, including the discrete Hartley transform (DHT), discrete sine transform (DST), and discrete cosine transform (DCT). First, succinct and unrestrictive Clenshaw's recurrence formula along with the inherent symmetry of the trigonometric functions are adequately employed to render efficient recurrences for computing these 1-D RDTT. By utilizing an appropriate row-column decomposition approach, the same set of recurrences can also be used to compute both of the row transform and column transform of the 2-D RDTT. Array architectures, basing on the developed recurrences, are then introduced to implement these 1-D and 2-D RDTT. Both architectures provide substantial hardware savings as compared with previous works. In addition, they are not only applicable to the 1-D and 2-D RDTT of arbitrary size, but they can also be easily adapted to compute all aforementioned RDTT with only minor modifications. A complete set of input/output (I/O) buffers along with a bidirectional circular shift matrix are addressed as well to enable the architectures to operate in a fully-pipelined manner and to rectify the transformed results in a natural order. Moreover, the resulting architectures are both highly regular, modular, and locally-connected, thus being amenable to VLSI implementations.

This paper describes the benefit of utilizing the unary function generators in a multiple-valued Programmable Logic Array (PLA). We will clarify the most suitable PLA structure in terms of the array size. The multiple-valued PLA considered here has a structure with two types of function generators (literal and unary function generators), a first-level array and a second-level array. On investigating the effectiveness to reduce the array size, we can pick up four form PLAs: MAX-of-TPRODUCT form, MIN-of-TSUM form, TSUM-of-TPRODUCT form and TPRODUCT-of-TSUM form PLAs among possible eight form PLAs constructing from the MAX, MIN, TSUM and TPRODUCT operators. The upper bound of the array sizes with v UGs is derived as (log2ppv + p(n-v) + 1) pn-1 to realize any n-variable p-valued function. Next, experiments to derive the smallest array sizes are done for 10000 randomly generated functions and 21 arithmetic functions. These results conclude that MAX-of-TPRODUCT form PLA is the most useful in reducing the array size among the four form PLAs.

Using Hopfield-type neural network model, we present an algorithm for reconstructing 3D mesh processor arrays using single-track switches where spare processors are laid on the six surfaces of a 3D array and show its effectiveness in terms of reconstruction rate and computing time by computer simulation. Next, we show how the algorithm can be realized by a digital neural circuit. It consists of subcircuits for finding candidate compensation paths, deciding whether the neural system reaches a stable state and at the time the system energy is minimum, and subcircuits for neurons. The subcircuit for each neuron including the other subcircuits can only be made with 16 gates and two flip-flops. Since the state transitions are done in parallel, the circuit will be able to find a set of compensation paths for a fault pattern very quickly within a time less than 1 µs. Furthermore, the hardware implementation of the algorithm leads to making a self-reconfigurable system without the aid of a host computer.

This paper describes a spatial spectral subtraction method by using the complementary beamforming microphone array to enhance noisy speech signals for speech recognition. The complementary beamforming is based on two types of beamformers designed to obtain complementary directivity patterns with respect to each other. In this paper, it is shown that the nonlinear subtraction processing with complementary beamforming can result in a kind of the spectral subtraction without the need for speech pause detection. In addition, the optimization algorithm for the directivity pattern is also described. To evaluate the effectiveness, speech enhancement experiments and speech recognition experiments are performed based on computer simulations under both stationary and nonstationary noise conditions. In comparison with the optimized conventional delay-and-sum (DS) array, it is shown that: (1) the proposed array improves the signal-to-noise ratio (SNR) of degraded speech by about 2 dB and performs more than 20% better in word recognition rates under the conditions that the white Gaussian noise with the input SNR of -5 or -10 dB is used, (2) the proposed array performs more than 5% better in word recognition rates under the nonstationary noise conditions. Also, it is shown that these improvements of the proposed array are same as or superior to those of the conventional spectral subtraction method cascaded with the DS array.

This paper reports on time-space conversion-based differential processing of optical signals using a high-resolution arrayed-waveguide grating (AWG) and a spatial filter at a wavelength of 1.55 µm. We clarify the advantages of the AWG device and show where it is applicable. In order to reduce loss at the spatial filter, we propose a new phase-only filter that functions as a differential filter. The difference between the exact differential filter and the proposed phase-only filter is calculated theoretically. We confirm experimentally that the optical pulse can be differentiated by the proposed filter. For application of differential processing, we also proposed a phase modulation to amplitude modulation (PM-AM) conversion and demonstrated the PM-AM conversion at 10 Gbit/s signals using a PSK-non-return-to-zero (NRZ) format.

In this paper, we present a novel architecture named as Window-MSPA architecture which targets to window operations in image processing. We have previously developed a Memory Sharing Processor Array (MSPA) for fast array processing with regular iterative algorithms. Window-MSPA tries to optimize the data I/O ports and the number of processing elements so as to reduce hardware cost. The input scheme of image data is restricted to row by row input which simplifies the I/O architecture. Under this practical I/O restriction, the fastest processings are achieved. In this paper, we present the general Window-MSPA design methodology for wide variety of applications. As an practical application, we have already reported the design of MP@HL MPEG2 Motion Estimator LSI. Design formulas for Window-MSPA architecture are given for various size of window operations in image processing. Thus, the derived architecture is flexible enough to satisfy user's requirement for either area or speed.