A more judicious choice of trial functions to implement the Improved Circuit Theory (ICT) application to multi-element antennas is achieved. These new trial functions, based on Tai's modified variational implementation for single element antennas, leads to an ICT implementation applicable to much longer co-planar dipole arrays. The accuracy of the generalized impedance formulas is in good agreement with the method of moments. Moreover, all these generalized formulas including the radiation pattern expressions are all in closed-form. This leads to an ICT implementation which still requires much shorter CPU time and lesser computer storage compared to method of moments. Thus, for co-planar dipole arrays, the proposed implementation presents a relatively very efficient method and would therefore be found useful in applications such as CAD/CAE systems.

An adaptive array has been proposed as a canceller for both inter-symbol interference (ISI) and co-channel interference (CCI). However, it has no path-diversity gain since it selects just one signal correlated to the reference signal. In this paper, a novel interference canceller having sufficient path-diversity gain is proposed. The canceller is characterized by the combined configuration of an adaptive array and an equalizer. In the proposed system, a pre-selecting adaptive array is installed first. By employing a specific training sequence and sampling timing at the receiver during the training period, the perfect correlation between the "desired signal" and "short delayed" is achieved. Therefore, the pre-selecting adaptive array can extract the desired and ISI signals simultaneously, and the cascaded adaptive equalizer can provide the path-diversity gain without degradation by interference. The proposed system achieves a simple configuration and robustness against both ISI and CCI with a sufficient path diversity gain. In computer simulations, average BER characteristics of the proposed system were evaluated in a quasi-static Rayleigh fading channel. The simulation results showed that the system can reduce both long-delayed ISI and CCI efficiently, and that the expected path diversity gain is obtained even with strong CCI. They also showed that the degradation is not so serious when the number of antenna elements is less than that of incoming signals.

We demonstrate an electrooptic synthesis technique for generating arbitrarily shaped short optical pulses from a CW narrow linewidth laser. For the optical pulse shaping, a large-amplitude electrooptic phase modulator is specially fabricated by employing the quasi-velocity-matching. The phase modulated light having sidebands as wide as 1 THz is separated and phase-only-controlled spatially by a liquid crystal modulator array. After composing the light by using a grating, nearly 1. 2 ps of Fourier-transform-limited optical pulses is obtained.

This paper presents two types of two-dimensional (2-D) adaptive beamforming algorithm which have high rate of convergence. One is a linearly constrained minimum variance (LCMV) beamforming algorithm which minimizes the average output power of a beamformer, and the other is a generalized sidelobe canceler (GSC) algorithm which generalizes the notion of a linear constraint by using the multiple linear constraints. In both algorithms, we apply a 2-D lattice filter to an adaptive filtering since the 2-D lattice filter provides excellent properties compared to a transversal filter. In order to evaluate the validity of the algorithm, we perform computer simulations. The experimental results show that the algorithm can reject interference signals while maintaining the direction of desired signal, and can improve convergent performance.

In this paper, we present an analytic model to study the reliability of some important disk array organizations that have been proposed by others in the literature. These organizations are based on the combination of two options for the data layout, regular RAID-5 and block designs, and three alternatives for sparing, hot sparing, distributed sparing and parity sparing. Uncorrectable bit errors have big effects on reliability but are ignored in traditional reliability analysis of disk arrays. We consider both disk failures and uncorrectable bit errors in the model. The reliability of disk arrays is measured in terms of MTTDL (Mean Time To Data Loss). A unified formula of MTTDL has been derived for these disk array organizations. The MTTDLs of these disk array organizations are also compared using the analytic model. By numerical experiments, we show that the data losses caused by uncorrectable bit errors may dominate the data losses of disk array systems though only the data losses caused by disk failures are traditionally considered. The consideration of uncorrectable bit errors provides a more realistic look at the reliability of the disk array systems.

Various high-performance SOI CMOS circuits were fabricated using fully-depleted 0.25-µm gate MOSFETs on a low-dose SIMOX substrate. 2.4-Gbps operations were achieved for I/O and speed conversion circuits which are key elements in a multimedia communication LSI. LVTTL-compatible gate array LSI was developed with an ESD protection circuit which is the first one to meer the MIL standard. A 120-kG test LSI was fabricated on the gate array, and the LSI performances using three kind of technologies; 0.25-µm bulk and SIMOX and 0.5-µm bulk; were compared. A 0.25-µm SIMOX LSI was 10% faster with 35% less power dissipation compared with a 0.25-µm bulk LSI. The 0.25-µm SIMOX LSI can operate at a VDD of 1.2 V to attain the same speed as the 0.5-µm bulk LSI operating at 3.3 V, and this results in 1/40 power reduction. For the high-speed communication use, an ATM-switch LSI with 220-kG and a 110-kb memory was fabricated. A high-performance of 2.5-Gbps interface speed and 312-Mbps internal speed were achieved using 0.25-µm CMOS/SIMOX. This ATM-switch LSI has the greatest bandwidth of 40-Gbps ever reported using a one-chip ATM-switch LSI.

Pilot symbol-assisted (PSA) decision-directed coherent adaptive array diversity (CAAD) is proposed for increasing the reverse link capacity of DS-CDMA mobile radio systems. In the proposed scheme, PSA channel estimation is applied to coherent Rake combining, and the weights of the antenna array are adaptively updated using both pilot symbols and decision-directed data symbols after Rake combining as references for minimum mean squared error (MMSE) criteria. The reverse link capacity of a 3-sectored base station is evaluated by computer simulation when fast transmit power control (TPC) based on singal-to-interference plus backgound noise power ratio (SIR) measurement is applied under nultipath Rayleigh fading environments. It is shown that a 6-element (sector) CAAD receiver can increase the capacity to about 4.2 times that with a single antenna (per sector) receiver when links are interference-limited. The link capacity achievable with the 6-element CAAD receiver is 1.2 times that with a 6-branch antenna diversity reciever with antenna spacing of 10 carrier wavelengths, while significantly reducing the strong interference from high bit rate transmission (high transmit power) users.

This letter proposes and investigates a method of estimating the direction of arrival (DOA) of wideband signals such as spread spectrum signals, in a multipath channel. The DOA estimation method can reduce the effect of signal distortion due to bandwidth of signals by creating a spatial spectrum wihch satisfies the sampling theory in the time domain. The DOA estimate calculated from this spatial spectrum is robust against signal distortion due to multipath. Computer simulations numerically evaluate the proposed method. In comparison with conventional MUSIC algorithm, the proposed method achieves superior performance in a multipath channel.

A rigorous analysis of coupling between two twin-slot antennas using the Finite Difference Time Domain (FDTD) method is reported for the first time. The Phase Cancellation Effect (PGE) is used to reduce the coupling due to the TM0 surface wave mode between the Coplanar Waveguide (CPW) fed cascade-connected twin-slot antennas. To confirm the effectiveness of this approach, coupling between single-slot and twin-slot elements separated by λ0/2 was analysed. The coupling between the two single-slot antennas was S21 = -30.2 dB. For the case of two twin-slot antennas, the coupling was found to be -37.8 dB, 7.6 dB below that of the single-slot antennas. The phase cancellation effect of surface waves is significant in reducing coupling between two twin-slot antennas, in addition to minimising power loss into substrate modes. A memory optimised implementation of the FDTD method with the Berenger Perfectly Matched Layer (PML) Absorbing Boundary Condition (ABC) was used for the numerical analysis.

We consider the problem of estimating one- and two-dimensional direction of arrivals for arbitrary plane waves in an incoherent/coherent source environment. For the one-dimensional case, we use matrix pencil (MP) method developed by Y. Hua for signal-poles estimation. We then extend this method to estimate the two-dimensional direction of arrivals (2D-DOA), resulting in the "Extended Matrix Pencil" (EMP) method. This method can be applied successfully as much for an incoherent source environment as for a coherent source environment. To study the performance of these methods, in both cases results are compared with the "Total Least Squares-Estimation of Signal Parameters via Rotational Invariance Techniques" (TLS-ESPRIT) and the "Spatial Smoothing-TLS-ESPRIT" (SS-TLS-ESPRIT) methods. The results show that the MP method estimates the DOA more accurately and better than the TLS-ESPRIT and the SS-TLS-ESPRIT, even with few snapshots. Simulation results show that the EMP method, presented in this paper, estimates the 2-DOA better than the other two methods used for comparison.

A method for recovering the LPC spectrum from a microphone array input signal corrupted by less directional ambient noise is proposed. This method is based on the subspace method, in which directional signal and non-directional noise is classified in the subspace domain using eigenvalue analysis of the spatial correlation matrix. In this paper, the coherent subspace (CSS) method, a broadband extension of the subspace method, is employed. The advantage of this method is that is requires a much smaller number of averages in the time domain for estimating subspace, suitable feature for frame processing such as speech recognition. To enhance the performance of noise reduction, elimination of noise-dominant subspace using projection is further proposed, which is effective when the SNR is low and classification of noise and signals using eigenvalue analysis is difficult.

The integral kernel expansion method is applied to an analysis of scattering of magnetostatic forward volume waves (MSFVWs) by an array with any number of metal strips. In this method, first the integral kernel of the Fourier integral is expanded in terms of orthogonal polynomials to obtain moment equations. Then a system of algebraic equations is derived by applying the Galerkin's method. In the process, interaction between strips is naturally taken into account and real current distributions on the strips are determined such that boundary conditions are satisfied. Calculus confirmation through the energy conservation principle shows that numerical results are quite satisfactory. A comparison shows that theoretical results are in good agreement with experimental ones except the vicinity of lower and upper limits of the MSFVW band. It is shown that an infinite number of propagation modes is excited even if a wave of single mode is incident. Dependence of the scattering on dimension of arrays and on frequency and mode of an incident wave is obtained.

The FPGA logic synthesis consists of logic minimization step and technology mapping step. These two steps are usually performed separately to reduce the complexity of the problem. Conventional logic minimization methods try to minimize the number of literals of a given Boolean network, while FPGA technology mapping techniques attempt to minimize the number of basic blocks. However, minimizing the number of literals, which is target architecture-independent feature, does not always lead to minimization of basic block count, which is a FPGA architecture specific feature. Therefore, most of the existing technology mapping systems take into account reorganization of its input circuits to get better mapping results. Such a loosely coupled logic synthesis paradigm may cause difficulties in finding the optimal solution. In this paper, we propose a new logic synthesis approach where logic minimization and technology mapping steps are performed tightly coupled. Our system takes into account FPGA specific features in logic minimization step and thus our technology mapping step does not need to resynthesize the Boolean network. We formulate the technology mapping problem as a graph covering problem. Such formulation provides more global view to optimality and supports versatile cost functions. in addition, a fast and exact library management technique is devised for efficient FPGA cell matching which is one of the most frequently used operations in the FPGA logic synthesis.

This paper proposes a new approach that makes it possible for every undergraduate student to perform experiments of developing a Ipipelined RISC processor within limited time available for the course. The approach consists of 4 steps. At the first step, every student implements by himself/herself a pipelined RISC processor which is based on a given, very simple model; it has separate buses for instruction and data memory ("Harvard architecture") to avoid structural hazard, while it completely ignores data control hazards to make implementation easy. Although it is such a "defective" processor, we can test its functionality by giving object code containing sufficient amount of NOP instructions to avoid hazards. At the second step, NOP instructions are deleted and behavior of the developed processor is observed carefully to understand data and control hazards. At the third step, benchmark problems are provided, and every student challenges to improve its performance. Finally every student is requested to present how he/she improved the processor. This paper also describes a new educational FPGA board ASAver.1 which is useful for experiments from introductory class to computer architecture/system class. As a feasibility study, a 16-bit pipelined RISC processor "ASAP-O" has been developed which has eight 16-bit general purpose registers, a 16-bit program counter, and a zero flag, with 10 essential instructions.

We have previously proposed a scannable memory configuration which is useful in testing logic blocks around memory arrays. Although the configuration is supposed to be effective in testing the memory array itself by its frequent read/write access during the scan operation, it has not been theoretically shown what types of faults can be detected. In this paper, from a viewpoint of memory testing, we investigate the testability of the scannable memory configuration and propose a memory array test using the scan path. It is shown that we can detect (1) all stuck-at faults in memory cells, (2) all stuck-at faults in address decoders, (3) all stuck-at faults in read/write logic, (4) static, dynamic and 2-coupling faults between memory cells of adjacent words, and (5) static coupling faults between memory cells in the same word. The test can be accomplished simply by comparing scan-in data and scan-out data. The test vector is 20ms bit long, where m is the number of words of the memory array under test and s is the total scan path length.

We report the strong microwave Josephson radiation from an array of high-Tc junctions on a MgO bicrystal substrate from centimeter- to millimeter-wave ranges. The dc bias current was fed to the junction array having parallel geometry with the pair of junctions shunted by superconducting loops. The configuration of bias leads was a series of interlocking dc SQUID's geometry which guaranteed the oscillation of all junctions at the same frequency. For a five-junctions array, we observed the coherent output power of about 13 pW at receiving frequency fREC22GHz without an external magnetic flux, which was nearly five times higher than that of a single bicrystal junction. We observed the Josephson linewidth of the selfradiation in coherent state less than 1 GHz by the adjustment of the external flux. The phase differences between adjacent junctions with different IcRn products could be controlled by an external small magnetic field. Submillimeter-wave detector response of the five-junction array was also studied experimentally at frequency f478 GHz.

The authors previously proposed a reconfigurable architecture called the "XL-scheme" in order to cope with processor element (PE) faults as well as link faults. However, they described an algorithm for compensating only for link faults. They determined the potential ability to tolerate faults of the XL-scheme for simultaneous faults of links and PEs, and left a reconstruction algorithm for simultaneous PE and link faults to be studied in the future. This paper briefly explains the XL-scheme and gives a reconstruction algorithm for simultaneous PE and link faults. The algorithm first replaces faulty PEs with healthy ones and then replaces faulty links with healthy ones. We then compute the reliabilities of the mesh-arrays with simultaneous PE and link faults by simulation. We compare the reliability of the XL-scheme with that of the one-and-half track switch model. It is seen that the former is much larger than the latter. Furthermore, we show the result for processing time.

Linear programming techniques are useful in many diverse applications such as: production planning, energy distribution etc. To find an optimal solution of the linear programming problem, we have to repeat computations and it takes a lot of processing time. For high speed computation of linear programming, special purpose hardware has been sought. This paper proposes a systolic array for solving linear programming problems using the revised simplex method which is a typical algorithm of linear programming. This paper also proposes a modified systolic array that can solve linear programming problems whose sizes are very large.

We have developed a Beam Space CMA (Constant Modulus Algorithm) Adaptive Array Antenna system (BSCMA adaptive array antenna) that may be suitable for mobile communications. In this paper, we present experimental results of interference cancellation characteristics using the developed system. The experiment was carried out in a large radio anechoic chamber, while desired and interference signals were transmitted to the system. We focused on the characteristics of capture, convergence and tracking in adaptive processing. The experimental results show excellent interference cancellation characteristics, and demonstrate that the BSCMA adaptive array antenna has a greater feasibility to be applied practically in mobile communications.

Several types of transmission-line coupling are analyzed to use in one- and two-dimensional active antenna arrays, and a method is developed to scan the beam of the arrays using the mutual locking theory. To compensate the undesired effect of strong radiative coupling of the nearest neighbor elements on the phased array performance, addition of resistive stubs to the end elements is proposed. In a 14 array it was observed that after the connection of resistive stubs, the scanning range of the array increased considerably. The effect of oscillator amplitudes on the phased array behavior is explored numerically. In the experiments main beam of 22 and 33 active antenna arrays were steered up to 25 and 15, respectively in the H-plane.