UNcorrectable Bit Errors (UNBEs) are important in considering the reliability of Redundant Array of Inexpensive Disks (RAID). They, however, have been ignored or have not been studied in detail in existing reliability analysis of RAID. In this paper, we present an analytic model to study the reliability of declustered-parity RAID by considering UNBEs. By using the analytic model, the optimistic and the pessimistic estimates of the probability that data loss occurs due to an UNBE during the data reconstruction after a disk failed (we call this DB data loss) are obtained. Then, the optimistic and the pessimistic estimates of the Mean Time To Data Loss (MTTDL) that take into account both DB data loss and the data loss caused by double independent disk failures (we call this DD data loss) are obtained. Furthermore, how the MTTDL depends on the number of units in a parity stripe, rebuild time of a failed disk and write fraction of data access are studied by numerical analysis.

This paper describes the characteristics of a one dimensional narrow-wall slotted waveguide array with a single-layer linear-to-circular polarization converter consisting of a dipole array. An external boundary value problem of one slot and three dipoles, which approximates the mutual coupling between the dipole array and an edge slot extending over three faces of a rectangular waveguide, is formulated and analyzed by the method of moments; design of polarization conversion is conducted for this model as a unit element. If every unit element has perfect circular polarization, grating lobes appear in the array pattern due to the alternating slot angle: these are suppressed in this paper by changing the dipole angle and degrading the axial ratio of the unit element. The validity of the design is confirmed by the measurements. The dipole array has negligible effects upon slot impedance; the polarization conversion for existing narrow-wall slotted arrays is realized by add-on dipole array.

To enhance fabrication yield for processor arrays, many reconfiguration schemes for replacing faulty processing elements (PE's) with spare PE's have been proposed. An array grid model based on single-track switches is one of such models. For this model, some algorithms for reconfiguring processor arrays have been proposed. However, any algorithm which can reconfigure the array, whenever the array is reconfigurable, has not been proposed as yet. This paper describes reconfiguration methods of processor arrays with faulty PE's. The methods use indirect replacements for reconfiguring arrays. First, we introduce a concept of fatal fault pattern, which makes an array unreconfigurable. Then, for the reconfiguration method with fixed spare arrangement, efficient spare arrangements are given by evaluating the probability of an occurring fatal fault pattern. Furher, we present reconfiguration algorithm with relocating spare. In the algorithm, fatal fault patterns are eliminated by relocating spare. Computer simulations show that the method has good performance of reconfiguration.

In contrast to previous algorithms for reconfiguring processor arrays under the assumption that spare rows and columns are placed on the perimeter of the array or on fixed positions, our new algorithm employs movable and partitionable spare rows and columns. The objective of moving and partitioning spare rows and/or columns is the elimination of faulty processors each of which is blocked in all directions to spare processors. The results of our computer simulation indicate that reconfigurability can significantly be improved.

A two-dimensional receiver OEIC array having an address selector for highly parallel interprocessor networks has been realized. The receiver OEIC array consists of two-dimensionally arranged 1616 (256) optical receiver cells with switching transistors, address selectors (decoders), and a comparator. Each optical receiver comprises a pin PD and a transimpedance-type HBT amplifier. The HBT has an InP passivation structure to suppress the emitter-size effect, which results in the improvement of current gains, especially at low collector current densities. The receiver OEIC array was fabricated on a 3-inch diameter InP substrate with pin/HBT integration technology. Due to the function of address selection, only one cell is activated and the other cells are mute, so the receiver OEIC array shows low crosstalk and low power consumption characteristics. The array also shows a 266-Mb/s data transmission capability. This receiver OEIC array is a most complex InP-based OEIC ever reported. The realization of the two-dimensional receiver OEIC array promises the future interprocessor networks with highly parallel optical interconnections.

Silica-based planar lightwave circuits (PLCs) are reviewed in terms of WDM applications. Four types of basic multiplexer are described and compared. Some topical applications of these multiplexers are introduced with their WDM systems. We conclude that because of these various applications, silica-based PLCs will play an important role in future WDM systems.

Wavelength Division Multiplexing (WDM) technology provides many options to the design of flexible alloptical networks. To exploit these options to their full potential, Photonic Integrated Circuits (PICs) for wavelength routing and switching will be indispensable. One of the basic building blocks of such PICs is the planar phased-array (PHASAR) wavelength demultiplexer. The monolithic integration of PHASARs with photodetectors, amplifiers, and other waveguide-based (passive) components is discussed.

Recently, a wavelength division multi/demultiplexing system has been viewed with keen interest because it is possible to increase the transmission capacity and system flexibility. An arrayed waveguide grating (AWG) type of Multi/demultiplexer which is one of the key components to realize such a system has been developed by using Planar Lightwave Circuits (PLCs). Newly designed optical circuits have been incorporated into the AWG to control the center wavelength and to expand the pass band width. The 3 dB pass band width is 1.4 times that of a conventional AWG. It is confirmed that the newly developed AWG has low polarization dependence, low temperature dependence and high reliability.

The characteristics of high-performance InP-based monolithically integrated single and multiple channel photoreceivers with an InGaAs p-i-n photodiode and InAlAs/InGaAs HBTs, realized by one-step molecular beam epitaxy, are described. The monolithically integrated photoreceiver includes an integrated spiral inductor following the p-i-n diode at the input of the transimpedance amplifier to enhance the circuit response at high frequencies. Crosstalk of the multi-channel photoreceiver arrays is greatly reduced by applying both a metal ground shield and dual bias. The maximum measured -3 dB bandwidth of a single-channel integrated p-i-n/HBT photoreceiver is 19.5 GHz and the minimum crosstalk of the photoreceiver arrays, with an individual channel bandwidth of 11.5 GHz, is 36 dB. At these performance levels, these OEICs represent the state-of-the-art in multichannel integrated photoreceiver arrays.

This paper presents the beam forming characteristics of an optical waveguide-type phased array antenna. Four linearly arranged array antenna was monolithically fabricated on one LiNbO3 substrate containing variable power dividers (VPDs) and optical phase shifters (OPSs). The amplitude and the phase of each antenna element was controlled by applying DC voltage on each VPD and OPS. Open ends of Ti-indiffused waveguides were used as antenna elements. This antenna was designed to operate at 1.3 µm wavelength band. Experimental results confirm the good beam forming capability of optical phased array antennas.

In this paper the design of systolic array processors for computing 2-dimensional Discrete Fourier Transform (2-D DFT) is considered. We investigated three different computational schemes for designing systolic array processors using systematic approach. The systematic approach guarantees to find optimal systolic array processors from a large solution space in terms of the number of processing elements and I/O channels, the processing time, topology, pipeline period, etc. The optimal systolic array processors are scalable, modular and suitable for VLSI implementation. An application of the designed systolic array processors to the prime-factor DFT is also presented.

The number of DRAMs that have adopted hierarchical word-line architecture has increased as developed DRAM memory capacity has increased to more than 64 Mb. Use of the architecture enhances many kinds of DRAM performances, such as access time and fabrication process margin. However, the architecture does cause some problems. This paper describes some kinds of hierarchical word-line circuitries that have been proposed. It also describes a partial subarray activation scheme that is combined with hierarchical word-line and data-line architectures and discusses their potential and required specifications for future multi-giga bit DRAMs.

It is shown that two-dimensional linear phase FIR digital filters with various shapes of frequency response can be designed and realized as modular array structures free of multiplier coefficients. The design can be performed by judicious selection of two low order linear phase transfer functions to be used at each module as kernel filters. Regular interconnection of the modules in L rows and K columns conditioned with boundary coefficients 1, 0 and 1/2 results in higher order digital filters. The kernels should be chosen appropriately to, first, generate the desired shape of frequency response characteristic and, second, lend themselves to multiplierless realization. When these two requirements are satisfied, the frequency response can be refined to possess narrower transition bands by adding additional rows and columns. General properties of the frequency response of the array are investigated resulting in Theorems that serve as valuable tools towards appropriate selection of the kernels. Several design examples are given. The array structures enjoy several favorable features. Specifically, regularity and lack of multiplier coefficients makes it suitable for high-speed systolic VLSI implementation. Computational complexity of the structure is also studied.

We developed a 1200 dots-per-inch light emitting diode array (1200 dpi LED array) chip using a GaAs0.8 P0.2 epitaxial substrate for the first time. One LED array chip consists of 256 LEDs. In general, LED arrays are fabricated by vapor-phase zinc diffusion. From the viewpoint that shallow junctions should be formed to fabricate a very high-density LED array, solid-phase diffusion seems to be more suitable. We fabricated the LED array using selectively-masked solid-phase zinc diffusion, and the diffusion depth was controlled at 1 µm. The diffusion depth was uniform under the diffusion window. The ratio of the length of lateral diffusion to the diffusion depth was about 1.7. These features imply that Zn diffusion was well controlled. In the Zn diffusion, the carrier concentration in the Zn diffusion region was high enough and the sheet resistance of the diffusion region with a diffusion depth of 1 µm was low enough to obtain a sufficient level of emitted light power. The results of performance tests showed that the characteristics of the LED array chip are satisfactory for application in optical printer print heads, because of the array's highly-resolved near-field pattern characteristic, ample emitted light power, low emitted-light-power deviation, and long life.

This paper describes the design and evaluation of fully scannable embedded memory arrays. A memory array, such as a register file, is made scannable by adding a small auxiliary circuit including a counter and multiplexers. Plural memory arrays can be chained into a single scan path along with ordinary flip-flops. Detailed configuration and implementation of the scannable CMOS and bipolar LCML register file macros are discussed. The overhead ratio of the CMOS register file macro with 16-word by 16-bit results in an 8.6% transistor count and a 6.4% die area. The access time overhaead is 7.8% and the set-up time increases by about 50ps. Bipolar LCML register file macros have been applied to gate array LSIs which have successfully achieved average stuck-at fault coverage of 99.2%.

We have developed and operated a newly conceived multiprobe scanning force microscope (SFM) using microfabricated piezoelectric cantilevers. An array of piezoelectric microcantilevers with a piezoelectric ZnO layer on an SiO2 film makes it possible to build a multiprobe SFM system. Multiprobe SFMs are required for the application of SFM to the probe lithography and high density data storage. Each cantilever probe of multiprobe system should have a detector for sensing of its own deflection and an actuator for positioning of its tip. The piezoelectric cantilever can detect its own vibration amplitude by measuring the piezoelectric current, and it can also drive its tip by applying a voltage to the piezoelectric layer. Therefore, the piezoelectric cantilever is suitable for each cantilever of the array in the multiprobe SFM. We have verified the applicability of the piezoelectric cantilever to each lever of the array by characterizing the sensitivities of the deflection sensing and actuation. The ZnO piezoelectric cantilever with the length of 125 µm works as the z scanner with the sensitivity of 20 nm/V. We have also fabricated an experimental piezoelectric microcantilever array with ten cantilevers. We have constructed parallel operation SFM system with two cantilevers of the fabricated array and successfully obtained parallel images of 1 µm pitch grating in constant height mode.

For quasi millimeter-wave and millimeter-wave high-speed wireless communications over wireless LANs and wireless ATMs, narrow beam antennas have been shown to provide high transmission quality by suppressing the troublesome multipath effect. However, the diameter of sector antennas needed to create the narrow beams rapidly increases with the sector number. In addition, the cylindrical shape of typical sector antennas does not suit portable terminals. This paper shows a methodology for designing planar sector antennas that overcomes these problems. The proposed antenna uses two kinds of beams and the antenna gains are equalized in all sectors. The antenna is developed as a 4-beam subarray fed by a planar Butler matrix circuit. The design method of the subarray and an evaluation of its characteristics in the 20 GHz band are discussed.

A slotted waveguide planar array using a single-layer feed circuit is applied to high frequency and high gain use. The remarkable efficiency of 75.6% is realized for the gain of 35.9 dBi in 22 GHz band and 64% is realized for 35.1 dBi in 60 GHz band. Each antenna consists of only two components; a slotted plate and a groove base plate, and are highly mass produceable.

In this paper, a design of a new processor array architecture with effective data storage schemes which meets the practical requirement of a reduced number of processor elements is proposed. Its design method is shown to be drastically simpler than the popular systolic arrays. This processor array which we call Memory Sharing Processor Array (MSPA) consists of a processor array, several memory units, and some address generation hardware units used to minimize the number of I/O ports. MSPA architecture with its design methodology tries to overcome overlapping data storages, idle processing time and I/O bottleneck problems, which mostly degrade the performance of systolic architecture. It has practical advantages over the systolic array in the view of area-efficiency, high throughput and practical input schemes.

A systematic procedure to configure faulttolerant systolic arrays based on Triplicated Triple Modular Redundancy is proposed. The design procedure consists of the triplication of the dependence graph which is formed from a target regular algorithm and the transformation onto physical time-processor domain. The resultant systolic arrays tolerate failures not only on processing elements but also on communication links. While it needs sophisticated connection scheme between processing elements to guarantee the fault-tolerance on communication links, the link complexity is possibly reduced by optimizing redundant operation scheme. Unconstrained and constrained link minimization problems are introduced, and the possibility and the constraints required for link complexity reduction are investigated.