It is shown that two-dimensional linear phase FIR digital filters with various shapes of frequency response can be designed and realized as modular array structures free of multiplier coefficients. The design can be performed by judicious selection of two low order linear phase transfer functions to be used at each module as kernel filters. Regular interconnection of the modules in L rows and K columns conditioned with boundary coefficients 1, 0 and 1/2 results in higher order digital filters. The kernels should be chosen appropriately to, first, generate the desired shape of frequency response characteristic and, second, lend themselves to multiplierless realization. When these two requirements are satisfied, the frequency response can be refined to possess narrower transition bands by adding additional rows and columns. General properties of the frequency response of the array are investigated resulting in Theorems that serve as valuable tools towards appropriate selection of the kernels. Several design examples are given. The array structures enjoy several favorable features. Specifically, regularity and lack of multiplier coefficients makes it suitable for high-speed systolic VLSI implementation. Computational complexity of the structure is also studied.

This paper presents the beam forming characteristics of an optical waveguide-type phased array antenna. Four linearly arranged array antenna was monolithically fabricated on one LiNbO3 substrate containing variable power dividers (VPDs) and optical phase shifters (OPSs). The amplitude and the phase of each antenna element was controlled by applying DC voltage on each VPD and OPS. Open ends of Ti-indiffused waveguides were used as antenna elements. This antenna was designed to operate at 1.3 µm wavelength band. Experimental results confirm the good beam forming capability of optical phased array antennas.

This paper describes the design and evaluation of fully scannable embedded memory arrays. A memory array, such as a register file, is made scannable by adding a small auxiliary circuit including a counter and multiplexers. Plural memory arrays can be chained into a single scan path along with ordinary flip-flops. Detailed configuration and implementation of the scannable CMOS and bipolar LCML register file macros are discussed. The overhead ratio of the CMOS register file macro with 16-word by 16-bit results in an 8.6% transistor count and a 6.4% die area. The access time overhaead is 7.8% and the set-up time increases by about 50ps. Bipolar LCML register file macros have been applied to gate array LSIs which have successfully achieved average stuck-at fault coverage of 99.2%.

We developed a 1200 dots-per-inch light emitting diode array (1200 dpi LED array) chip using a GaAs0.8 P0.2 epitaxial substrate for the first time. One LED array chip consists of 256 LEDs. In general, LED arrays are fabricated by vapor-phase zinc diffusion. From the viewpoint that shallow junctions should be formed to fabricate a very high-density LED array, solid-phase diffusion seems to be more suitable. We fabricated the LED array using selectively-masked solid-phase zinc diffusion, and the diffusion depth was controlled at 1 µm. The diffusion depth was uniform under the diffusion window. The ratio of the length of lateral diffusion to the diffusion depth was about 1.7. These features imply that Zn diffusion was well controlled. In the Zn diffusion, the carrier concentration in the Zn diffusion region was high enough and the sheet resistance of the diffusion region with a diffusion depth of 1 µm was low enough to obtain a sufficient level of emitted light power. The results of performance tests showed that the characteristics of the LED array chip are satisfactory for application in optical printer print heads, because of the array's highly-resolved near-field pattern characteristic, ample emitted light power, low emitted-light-power deviation, and long life.

We have developed and operated a newly conceived multiprobe scanning force microscope (SFM) using microfabricated piezoelectric cantilevers. An array of piezoelectric microcantilevers with a piezoelectric ZnO layer on an SiO2 film makes it possible to build a multiprobe SFM system. Multiprobe SFMs are required for the application of SFM to the probe lithography and high density data storage. Each cantilever probe of multiprobe system should have a detector for sensing of its own deflection and an actuator for positioning of its tip. The piezoelectric cantilever can detect its own vibration amplitude by measuring the piezoelectric current, and it can also drive its tip by applying a voltage to the piezoelectric layer. Therefore, the piezoelectric cantilever is suitable for each cantilever of the array in the multiprobe SFM. We have verified the applicability of the piezoelectric cantilever to each lever of the array by characterizing the sensitivities of the deflection sensing and actuation. The ZnO piezoelectric cantilever with the length of 125 µm works as the z scanner with the sensitivity of 20 nm/V. We have also fabricated an experimental piezoelectric microcantilever array with ten cantilevers. We have constructed parallel operation SFM system with two cantilevers of the fabricated array and successfully obtained parallel images of 1 µm pitch grating in constant height mode.

A slotted waveguide planar array using a single-layer feed circuit is applied to high frequency and high gain use. The remarkable efficiency of 75.6% is realized for the gain of 35.9 dBi in 22 GHz band and 64% is realized for 35.1 dBi in 60 GHz band. Each antenna consists of only two components; a slotted plate and a groove base plate, and are highly mass produceable.

In this paper, a design of a new processor array architecture with effective data storage schemes which meets the practical requirement of a reduced number of processor elements is proposed. Its design method is shown to be drastically simpler than the popular systolic arrays. This processor array which we call Memory Sharing Processor Array (MSPA) consists of a processor array, several memory units, and some address generation hardware units used to minimize the number of I/O ports. MSPA architecture with its design methodology tries to overcome overlapping data storages, idle processing time and I/O bottleneck problems, which mostly degrade the performance of systolic architecture. It has practical advantages over the systolic array in the view of area-efficiency, high throughput and practical input schemes.

A systematic procedure to configure faulttolerant systolic arrays based on Triplicated Triple Modular Redundancy is proposed. The design procedure consists of the triplication of the dependence graph which is formed from a target regular algorithm and the transformation onto physical time-processor domain. The resultant systolic arrays tolerate failures not only on processing elements but also on communication links. While it needs sophisticated connection scheme between processing elements to guarantee the fault-tolerance on communication links, the link complexity is possibly reduced by optimizing redundant operation scheme. Unconstrained and constrained link minimization problems are introduced, and the possibility and the constraints required for link complexity reduction are investigated.

Memory Sharing Processor Array (MSPA) architecture has been developed as an effective array processing architecture for both reduced data storages and increased processor cell utilization efficiency [1]. In this paper, the MSPA design methodology is extended to the VLSI synthesis of a serial input processor array (Pa). Then, a new bit-serial input multiplier and a new data serial input matrix multiplier are derived from the new PA. These multipliers are superior to the conventional multipliers by their smaller number of logic-gate count.

For quasi millimeter-wave and millimeter-wave high-speed wireless communications over wireless LANs and wireless ATMs, narrow beam antennas have been shown to provide high transmission quality by suppressing the troublesome multipath effect. However, the diameter of sector antennas needed to create the narrow beams rapidly increases with the sector number. In addition, the cylindrical shape of typical sector antennas does not suit portable terminals. This paper shows a methodology for designing planar sector antennas that overcomes these problems. The proposed antenna uses two kinds of beams and the antenna gains are equalized in all sectors. The antenna is developed as a 4-beam subarray fed by a planar Butler matrix circuit. The design method of the subarray and an evaluation of its characteristics in the 20 GHz band are discussed.

The polymer matrix for the number of N in-puts/outputs, N stages and 2x2-switches is denoted as the 1-D Spanke-Benes (SB) network. Throughout the paper, the 1-D SB-network, which equals the diamond cellular array, is extended to arbitrary dimensions by a mathematical transformation (a 1-D network provides the interconnection of 1-D data). This transformation determines the multistage architecture completely by providing size, location, geometry and wiring of the switches as well as it preserves properties of the networks, e.g., the capability of sorting. The SB-networks of dimension 3 are analysed and sorting is applied.

This paper presents a novel clock routing method used in constructing an optimal clock tree for embedded array chips by determining the route so as to minimize both delay and skew. The proposed method features constructing a tree by optimal node-pair merging, predicting the upper side balancedtree structure, based on accurate global path or delay estimation. By this method, in the case of the chip with large macro cells, the delay estimation error has been within 10%.

This paper verifies the accuracy of PO as applied to the scattering of dipole waves by a finite size reflector which is composed of strips on a grounded dielectric slab. By using the closed form expressions of reflected waves from the surface, PO calculation can be conducted straightforwardly. The calculated results are compared with the experimental ones for vertical and horizontal dipoles over a circular reflector.

44 matrix-based analysis of electromagnetic waves scattered by an infinite array of slots with polar-type anisotropic media are presented. In the analysis, the total fields are given as sum of the fields which exist even if the apertured plane are replaced by a ground plane and the fields scattered from the magnetic currents within the apertures. The scattered fields are expanded in terms of two-dimensional Floquet modes. Expression of each fields are obtained through eigenvalue problem for 44 coupled wave matrix. Unknown magnetic currents in the apertures are determined by applying Galerkin's method to the continuity condition about the magnetic fields in the apertures. Calculated results for isotropic cases are compared with other results for the complementary problem available in the literature using Babinet's principle. Further numerical calculations are performed in the case of gratings with polar-type anisotropic slab.

The Yasuura method is effective for calculating scattering problems by bodies of revolution. However dealing with 3-D scattering problems, we need to solve bigger size dense matrix equations. One of the methods to solve 3-D scattering is to use multipole expansion which accelerate the convergence rate of solutions on the Yasuura method. We introduce arrays of multipoles and obtain rapidly converging solutions. Therefore we can calculate scattering properties over a relatively wide frequency range and clarify scattering properties such as frequency dependence, shape dependence, and polarization dependence of 3-D scattering from perfectly conducting scatterer. In these numerical results, we keep at least 2 significant figures.

In this paper, we discuss problems in design and fault masking of multiple-valued cellular arrays where basic cells having simple switch functions are arranged iteratively. The stuck-at faults of switch cells are assumed to be fault models. First, we introduce a universal single-level array and derive the ratio of the number of single faults whose influence can be masked to the total number of single faults. Next, we propose a universal two-level array that outputs correct values even if single faults occur in it and derive the ratio of the number of double faults whose influence can be masked compared to the total number of double faults. By evaluating the universal single-level array and the universal two-level array from the viewpoints of design and fault masking, we show that the latter is superior to the former. Finally, we compare our universal two-level array with formerly presented arrays in order to demonstrate the advantages of our universal two-level array.

Resonant properties of resistance shunted tunnel junctions have been investigated using the RLCSJ model. We found that an increase in dc current resulted from an increase in impedance of the shunted tunnel junctions. The static and dynamic properties of the shunted tunnel junctions were described in detail by numerical simulations and experiments. The simulated and measured results showed good agreement in I-V characteristics. A Josephson array oscillator has been proposed using the resonant properties for increasing oscillator output impedance. We designed and fabricated the oscillator with 20 shunted tunnel junctions. The output power of the oscillator delivered to the load resistor was estimated to be about 0.5µW at 312 GHz.

Many numerical simulation problems of natural phenomena are formulated by large tridiagonal and block tridiagonal linear systems. In this paper, an efficient parallel algorithm to solve a tridiagonal linear system is proposed. The algorithm named bi-recurrence algorithm has an inherent parallelism which is suitable for parallel processing. Its time complexity is 8N - 4 for a tridiagonal linear system of order N. The complexity is little more than the Gaussian elimination algorithm. For parallel implementation with two processors, the time complexity is 4N - 1. Based on the bi-recurrence algorithm, a VLSI oriented tridiagonal solver is designed, which has an architecture of 1-D linear systolic array with three processing cells. The systolic tridiagonal solver completes finding the solution of a tridiagonal linear system in 3N + 6 units of time. A highly parallel systolic tridiagonal solver is also presented. The solver is characterized by highly parallel computability which originates in the divide-and-conquer strategy and high cost performance which originates in the systolic architecture. This solver completes finding the solution in 10(N/p) + 6p + 23 time units, where p is the number of partitions of the system.

In the design of a large slotted waveguide array, evaluation of mutual couplings between the slots is time consuming. This paper proposes an effective approximation analysis of the external mutual couplings using periodic boundary condition. Simple design procedure is verified for two-dimensional slot array.

The characteristics of a-Si bottom-gate TFT test devices with several kinds of inorganic "quasi-black matrix," such as metal, semiconductor, and insulator, on the top were investigated for various black matrix(BM) resistivities. In the Ia-Vg characteristics, for a BM sheet resistance of about1 1012 Ω/, a high off current and large Vth shift were observed due to the back-gating effects when the BM is charged up. Accrding to the ac dynamic characteristics, there was almost no leakage due to the capacitive coupling between source and drain after 16.6 msec(one frame) when the BM sheet resistance was above 7 1013 Ω/ . It was found that hydrogenated amorphous silicon germanium(a-SiGe:H) film, which has enough optical density, with the sheet resistance above the order of 1014 Ω/ is a promising candidate for an inorganic BM on TFT array.