This paper proposes an appearance-based novel descriptor for estimating head orientation. Our descriptor is inspired by the Weber-based feature, which has been successfully implemented for robust texture analysis, and the gradient which performs well for shape analysis. To further enhance the orientation differences, we combine them with an analysis of the intensity deviation. The position of a pixel and its intrinsic intensity are also considered. All features are then composed as a feature vector of a pixel. The information carried by each pixel is combined using a covariance matrix to alleviate the influence caused by rotations and illumination. As the result, our descriptor is compact and works at high speed. We also apply a weighting scheme, called Block Importance Feature using Genetic Algorithm (BIF-GA), to improve the performance of our descriptor by selecting and accentuating the important blocks. Experiments on three head pose databases demonstrate that the proposed method outperforms the current state-of-the-art methods. Also, we can extend the proposed method by combining it with a head detection and tracking system to enable it to estimate human head orientation in real applications.

In this study we investigate the synchronization of relaxation oscillators having individual differences by using non-periodic signal injection. When a common non-periodic signal is injected into the relaxation oscillators, the oscillators exhibit synchronization phenomena. Such synchronization phenomena can be classified as injection locking. We also consider the relation between the synchronization state and the individual difference. Further, we pay attention to the effect of the fluctuation range of the non-periodic injected signal. When the fluctuation range is wide, we confirm that the synchronization range increases if the individual difference is small.

Single-carrier (SC) transmission with space-time block coded (STBC) transmit diversity can achieve good bit error rate (BER) performance. However, in a high mobility environment, the STBC codeword orthogonality is distorted and as consequence, the BER performance is degraded by the interference caused by the orthogonality distortion of STBC codeword. In this paper, we proposed a novel frequency-domain equalization (FDE) for SC-STBC transmit diversity in doubly selective fading channel. Multiple FDE weight matrices, each associated with a different code block, are jointly optimized based on the minimum mean square error (MMSE) criterion taking into account not only channel frequency variation but also channel time variation over the STBC codeword. Computer simulations confirm that the proposed robust FDE achieves BER performance superior to conventional FDE, which was designed based on the assumption of a quasi-static fading.

Coordinate interleaved orthogonal design (CIOD) using four transmit antennas provides full diversity, full rate (FDFR) properties with low decoding complexity. However, the constellation expansion due to the coordinate interleaving of the rotated constellation results in peak to average power ratio (PAPR) increase. In this paper, we propose two signal constellation design methods which have low PAPR. In the first method we propose a signal constellation by properly selecting the signal points among the expanded square QAM constellation points, based on the co-prime interleaving of the first coordinate signal. We design a regular interleaving pattern so that the coordinate distance product (CPD) after the interleaving becomes large to get the additional coding gain. In the other method we propose a novel constellation with low PAPR based on the clipping of the rotated square QAM constellation. Our proposed signal constellations show much lower PAPR than the ordinary rotated QAM constellations for CIOD.

An on-chip monitoring circuit using a sub-sampling scheme, which consists of a 6-bit flash analog-to-digital converter (ADC) and a 51-phase phase-locked loop (PLL)-based frequency synthesizer, is proposed to analyze the signal integrity of a single-ended 8-Gb/s octal data rate (ODR) chip-to-chip interface with a source synchronous clocking scheme.

A cryptographic hash is an important tool in the area of a modern cryptography. It comprises a compression function, where the compression function can be built by a scratch or blockcipher. There are some familiar schemes of blockcipher compression function such as Weimar, Hirose, Tandem, Abreast, Nandi, ISA-09. Interestingly, the security proof of all the mentioned schemes are based on the ideal cipher model (ICM), which depends on ideal environment. Therefore, it is desired to use such a proof technique model, which is close to the real world such as weak cipher model (WCM). Hence, we proposed an (n, 2n) blockcipher compression function, which is secure under the ideal cipher model, weak cipher model and extended weak cipher model (ext.WCM). Additionally, the majority of the existing schemes need multiple key schedules, where the proposed scheme and the Hirose-DM follow single key scheduling property. The efficiency-rate of our scheme is r=1/2. Moreover, the number of blockcipher call of this scheme is 2 and it runs in parallel.

This paper introduces low-power and small area injection-locking clock and data recovery circuit (CDR) for the wireline and wireless proximity link. By using signal conversion from differential input to common-mode output, the newly proposed edge detector can eliminate the usually used delay line and XOR-based edge detector, and provided low power operation and a small circuit area. The CDR test chip fabricated in a 65-nm CMOS process consumes 30mW from a 1.2- V supply at 12.5Gbps. The fabricated CDR achieved a BER lower than 10-12 and the recovered clock had an rms jitter of 0.87ps. The CDR area is 0.165mm2.

This paper presents a varactor-based all-digital phase-locked loop (ADPLL) with a multi-phase digitally controlled oscillator (DCO) for near-threshold voltage operation. In addition, a new all-digital reference spur suppression (RSS) circuit with multiple phases random-sampling techniques to effectively spread the reference clock frequency is proposed to randomize the synchronized DCO register behavior and reduce the reference spur. Because the equivalent reference clock frequency is reserved, the loop behavior is maintained. The area of the proposed spur suppression circuit is only 4.9% of the ADPLL (0.038 mm2). To work reliably at the near-threshold region, a multi-phase DCO with NMOS varactors is presented to acquire precise frequency resolution and high linearity. In the near-threshold region (VDD =0.52 V), the ADPLL only dissipates 269.9 μW at 100 MHz output frequency. It has a reference spur of -52.2 dBc at 100 MHz output clock frequency when the spur suppression circuit is deactivated. When the spur suppression circuit is activated, the ADPLL shows a reference spur of -57.3 dBc with the period jitter of 0.217% UI.

In this letter, we propose a novel wear leveling technique we call Hidden cold block-aware Wear Leveling (HaWL) using a bit-set threshold. HaWL prolongs the lifetime of flash memory devices by using a bit array table in wear leveling. The bit array table saves the histories of block erasures for a period and distinguishes cold blocks from all blocks. In addition, HaWL can reduce the size of the bit array table by using a one-to-many mode, where one bit is related to many blocks. Moreover, to prevent degradation of wear leveling in the one-to-many mode, HaWL uses bit-set threshold (BST) and increases the accuracy of the cold block information. The performance results illustrate that HaWL prolongs the lifetime of flash memory by up to 48% compared with previous wear leveling techniques in our experiments.

A low-voltage controller-based all-digital phase-locked loop (ADPLL) utilized in the medical implant communication service (MICS) frequency band was designed in this study. In the proposed design, controller-based loop topology is used to control the phase and frequency to ensure the reliable handling of the ADPLL output signal. A digitally-controlled oscillator with a delta-sigma modulator was employed to achieve high frequency resolution. The phase error was reduced by a phase selector with a 64-phase signal from the phase interpolator. Fabricated using a 130-nm CMOS process, the ADPLL has an active area of 0.64 mm2, consumes 840 µW from a 0.7-V supply voltage, and has a settling time of 80 µs. The phase noise was measured to be -114 dBc/Hz at an offset frequency of 200 kHz.

Nearest-neighbor-search classifiers are attractive but they have high intrinsic computational demands which limit their practical application. In this paper, we propose a coprocessor for k (k with k≥1) nearest neighbor (kNN) classification in which squared Euclidean distances (SEDs) are mapped into the clock domain for realizing high search speed and energy efficiency. The minimal SED searching is carried out by weighted frequency dividers that drastically reduce the normally exponential increase of the worst-case search-clock number with the bit width of vector components to only a linear increase. This also results in low power dissipation and high area-efficiency in comparison to the traditional method using large numbers of adders and comparators. The kNN classifier determines the class of an unknown input sample with a majority decision among the k nearest reference samples. The required majority-decision circuit is integrated with the clock-mapping-based minimal-SED searching architecture and proceeds with the classification immediately after identification of each of the k nearest references. A test chip in 180 nm CMOS technology, which can process 8 dimensions of 32 reference vectors in parallel, achieves low power dissipation of 40.32 mW (at 51.21 MHz clock frequency and 1.8 V supply voltage). Significantly, the distance search circuit consumes only 5.99 mW. Feature vectors with different dimensionality up to 2048 dimensions can be handled by the designed coprocessor due to a dimension extension circuit, enabling large flexibility for usage in different application.

We numerically demonstrated the improvement of single-electron (SE) digital logic gates by utilizing SE input discretizers (IDs). The parameters of the IDs were adjusted to achieve SE tunneling at the threshold voltage designed for switching. An SE four-junction inverter (FJI) with an ID (ID-FJI) had steep switching characteristics between the high and low output voltage levels. The limiting temperature and the critical parameter margins were evaluated. An SE NAND gate with IDs also achieved abrupt switching characteristics between output logic levels.

This paper proposes an on-chip measurement method of PLL through fully digital interface. For the measurement of the PLL transfer function, we modulated the phase of the PLL input in triangular form using Digital-to-Time Converter (DTC) and read out the response by Time-to-Digital Converter (TDC). Combination of the DTC and TDC can obtain the transfer function of the PLL both in the magnitude domain and the phase domain. Since the DTC and TDC can be controlled and observed by digital signals, the measurement can be conducted without any high speed analog signal. Moreover, since the DTC and TDC can be designed symmetrically, the measurement method is robust against Process, Voltage, and Temperature (PVT) variations. At the same time, the employment of the TDC also enables a measurement of the PLL lock range by changing the division ratio of the divider. Two time domain circuits were designed using 180nm CMOS process and the HSPICE simulation results demonstrated the measurement of the transfer function and lock range.

This paper presents two new types of markers of M-CubITS (M-sequence Multimodal Markers for ITS; M-Cubed for ITS) that is a ground-based positioning system, in order to advance the WYSIWYAS (What You See Is What You Are Suggested) navigation environments providing intuitive guidance. One of the new markers uses warning blocks of textured paving blocks that are often at important points as for pedestrian navigation, for example, the top and bottom of stairs, branch points, and so on. The other uses interlocking blocks that are often at wide spaces, e.g., pavements of plazas, parks, sidewalks and so on. Furthermore, we construct the integrated pedestrian navigation system equipped with the automatic marker-type identification function of the three types of markers (the warning blocks, the interlocking blocks, and the conventional marker using guidance blocks of textured paving blocks) in order to enhance the spatial availability of the whole M-CubITS and the navigation system. Consequently, we show the possibility to advance the WYSIWYAS navigation environments through the performance evaluation and the operation confirmation of the integrated system.

In this letter, we propose a blind adaptive algorithm for joint compensation of inter-block interference (IBI) and frequency-dependent IQ imbalance using a single time-domain equalizer. We combine the MERRY algorithm for IBI suppression with the differential constant modulus algorithm to compensate for IQ imbalance. The effectiveness of the proposed algorithm is shown through computer simulations.

This paper presents the first non-trivial collision attack on the double-block-length compression function presented at FSE 2006 instantiated with round-reduced AES-256: f0(h0||h1,M)||f1(h0||h1,M) such that f0(h0||h1, M) = Eh1||M(h0)⊕h0 , f1(h0||h1,M) = Eh1||M(h0⊕c)⊕h0⊕c , where || represents concatenation, E is AES-256 and c is a 16-byte non-zero constant. The proposed attack is a free-start collision attack using the rebound attack proposed by Mendel et al. The success of the proposed attack largely depends on the configuration of the constant c: the number of its non-zero bytes and their positions. For the instantiation with AES-256 reduced from 14 rounds to 8 rounds, it is effective if the constant c has at most four non-zero bytes at some specific positions, and the time complexity is 264 or 296. For the instantiation with AES-256 reduced to 9 rounds, it is effective if the constant c has four non-zero bytes at some specific positions, and the time complexity is 2120. The space complexity is negligible in both cases.

This paper proposes Fast Fourier Transform (FFT) based orthogonal beam selection method at the user terminals (UTs) to reduce the number of nulls for the other users except an intended user by the Block Diagonalization (BD) algorithm in multiuser MIMO (MU-MIMO) sytems. The BD algorithm has been proposed in order to realize MU-MIMO broadcast transmission with a realistic signal processing burden. The BD algorithm cancels inter-user interference by creating the weights so that the channel matrixes for the other users are set to be zero matrixes. However, when the number of transmit antennas is equals to the total number of received antennas, the transmission rate by the BD algorithm is decreased. The proposed method realizes the performance improvement compared to the conventional BD algorithm without the burden on the UTs. It is verified via bit error rate (BER) evaluation that the proposed method is effective compared to the conventional BD algorithm and antenna selection method. Moreover, the effectiveness of proposed method is verified by the performance evaluation considering medium access control (MAC) layer in a comparison with the conventional BD algorithm which needs the channel state information (CSI) feedback. Because the proposed method can be easily applied to beamforming without the CSI feedback (implicit beamforming), it is shown that the propose method is effective from a point of view on the transmission efficiency in MU-MIMO system.

We present a low-voltage digitally-controlled oscillator (DCO) with the third-order ΔΣ modulator utilized in the medical implant communication service (MICS) frequency band. An optimized DCO core operating in the subthreshold region is designed, based on the gm/ID methodology. Thermometer coder with the dynamic element matching and ΔΣ modulator are implemented for the frequency tuning. High frequency resolution is achieved by using the ΔΣ modulator. The ΔΣ-modulator-based LC-DCO implemented in a 130-nm CMOS technology has achieved the phase noise of -115.3 dBc/Hz at 200 kHz offset frequency with the tuning range of 382 MHz to 412 MHz for the MICS band. It consumes 700 µW from a 0.7-V supply voltage and has a high frequency resolution of 18 kHz.

We propose the concept of an integrated coherent photonic wireless transmitter based on the simultaneous injection locking of two monolithically integrated distributed feedback (DFB) laser diodes (LDs) using an optical frequency comb (OFC). We characterize the basic operation of the transmitter and demonstrate that two injection-locked integrated DFB LDs are sufficiently stable to generate the carrier signal using a uni-traveling-carrier photodiode (UTC-PD) for a real-time error-free (bit error rate: BER < 10-11) coherent transmission with a data rate of 10 Gbit/s at a carrier frequency of 97 GHz. In the coherent wireless transmission, we compare the BER characteristics of the injection-locked transmitter with that of an actively phase-stabilized transmitter and show that the power penalty of 8-dB for the injection-locked transmitter is due to the RF spurious components, which can be reduced by integrating the OFC generator (OFCG) and LDs on the same chip. Our results suggest that the integration of the OFCG, DFB LDs, modulators, semiconductor optical amplifiers, and UTC-PD on the same chip is a promising strategy to develop a practical real-time ultrafast coherent millimeter/terahertz wave wireless transmitter.

High gain extinction ratio and stable control of the phase in phase sensitive amplification are fundamental to realize either phase regeneration or quadrature squeezing of phase modulated signals in an efficient and robust manner. In this paper, we show that a combination of our previously demonstrated “sideband-assisted” dual-pump phase sensitive amplifier with a gain extinction ratio of more than 25dB, and a phase-locked loop based stabilization technique, enable efficient QPSK quadrature squeezing. Its stable operation is exploited to realize phase de-multiplexing of QPSK signals into BPSK tributaries. The phase de-multiplexed signals are evaluated through measurement of constellation diagrams, eye diagrams and more importantly, BER curves. The de-multiplexed BPSK signals exhibited an OSNR penalty of less than 1dB compared to the back-to-back BPSK signals.