This paper presents an interconnect resilient (IR) methodology with maximal interconnect fault tolerance, yield, and reliability for both single and multiple interconnect faults under stuck-at and open fault models. By exploiting multiple routes inherent in an interconnect structure, this method can tolerate faulty connections by efficiently finding alternative paths. The proposed approach is compatible with previous interconnect detection and diagnosis methods under oscillation ring schemes, and together they can be applied to implement a robust interconnect structure that may still provide correct communication even under multiple link faults in Network-on-Chips (NoCs). With such knowledge, designers can significantly improve interconnect reliability by augmenting vulnerable interconnect structures in NoCs. As a result, the experimental results show that alternative paths in NoCs can be found for almost all paths. Hence, the proposed method provides a good way to achieve fault tolerance and reliability/yield improvement.

E-band low-noise amplifier (LNA) monolithic millimeter-wave integrated circuits (MMICs) were developed using pseudomorphic In0.75Ga0.25As/In0.52Al0.48As high electron mobility transistors (HEMTs) with a gate length of 50 nm. The nanogate HEMTs demonstrated a maximum oscillation frequency (fmax) of 550 GHz and a current-gain cutoff frequency (fT) of 450 GHz at room temperature, which is first experimental demonstration that fmax as high as 550 GHz are achievable with the improved one-step-recessed gate procedure. Furthermore, using a three-stage LNA-MMIC with 50-nm-gate InGaAs/InAlAs HEMTs, we achieved a minimum noise figure of 2.3 dB with an associated gain of 20.6 dB at 79 GHz.

Frequency dependent properties of accumulation-mode MOS varactors, which are key elements in many RF circuits, are dominated by Non-Quasi-Static (NQS) effects in the carrier transport. The circuit performances containing MOS varactors can hardly be reproduced without considering the NQS effect in MOS-varactor models. For the LC-VCO circuit as an example it is verified that frequency-tuning range and oscillation amplitude can be overestimated by over 20% and more than a factor 2, respectively, without inclusion of the NQS effect.

In this paper, a criterion for nonlinear stability analysis of microwave oscillator has been devised. The circuit envelope method has been used for analyzing the perturbed circuit. The proposed approach is evaluated by analyzing the nonlinear stability of a practical FET oscillator.

The C-oscillation due to Martin-Löf shows that {α| ∀ n [C(α n)≥ n-O(1)]=, which also follows {α| ∀ n [K(α n)≥ n+K(n)-O(1)]=. By generalizing them, we show that there does not exist a real α such that ∀ n (K(α n)≥ n+λ K(n)-O(1)) for any λ>0.

Testing is a critical stage in integrated circuits production in order to guarantee reliability. The complexity and high integration level of mixed-signal ICs has put forward new challenges to circuit testing. This paper describes an oscillation-based combined self-test strategy for the analog portion and analog-to-digital converters (ADCs) in integrated mixed-signal circuits. In test mode, the analog portion under test is reconfigured into an oscillator, generating periodic signals as the test stimulus of ADC. By analyzing the A/D conversion results, a histogram test of ADC can be performed, and the oscillation frequency as well as amplitude can be checked, and in this way the oscillation test of the analog portion is realized simultaneously. For an analog benchmark circuit combined with an ADC, triangle oscillation and sinusoid oscillation schemes are both given to test their faults. Experimental results show that fault coverage of the analog portion is 92.2% and 94.3% in the two schemes respectively, and faults in the ADC can also be tested.

An injection-locked clock recovery circuit (CRC) with quadrature outputs based on multiplexed oscillator is presented. The CRC can operate at a half-rate speed to provide an adequate locking range with reasonable jitter and power consumption because both clock edges sample the data waveforms. Implemented by 0.18-µm CMOS technique, experimental results demonstrate that it can achieve the phase noise of the recovered clock about -121.55 dBc/Hz at 100-kHz offset and -129.58 dBc/Hz at 1-MMz offset with 25 MHz lock range, while operating at the input data rate of 1.55 Gb/s.

In this paper, we consider a simple nonlinear system which consists of a chaotic system and multirate sample-hold controllers. The proposed system exhibits some stabilized Unstable Periodic Orbits which are embedded on the chaos attractor of the original chaotic system. We provide a condition to stabilize Unstable Periodic Orbits and its domain of attraction. Some theoretical results are verified in the experimental circuit.

In this letter, a 1.25-Gb/s 0.18-µm CMOS half-rate burst-mode clock and data recovery (CDR) circuit is presented. The CDR contains a fast-locking clock recovery circuit (CRC) using a realigned oscillation technique to recover the desired clock. To reduce the power dissipation, the CRC uses a two-stage ring structure and a current-reused concept to merge with an edge detector. The recovered clock has a peak-to-peak jitter of 34.0 ps at 625 MHz and the retimed data has a peak-to-peak jitter of 44.0 ps at 625 Mb/s. The occupied die area of the CDR is 1.41.4 mm2, and power consumption is 32 mW under a 1.8-V supply voltage.

Experimental result and theoretical analysis are reported for bias-voltage dependence of oscillation frequency in resonant tunneling diodes (RTDs) integrated with slot antennas. Frequency change of 18 GHz is obtained experimentally for a device with the central oscillation frequency of 470 GHz. The observed frequency change is attributed to the bias-voltage dependence of the transit time of electrons across the RTD layers, which results in a voltage-dependent capacitance added to RTD. Theoretical analysis taking into account this transit time is in reasonable agreement with the observed results. Voltage-controlled RTD oscillators in the terahertz range are expected from the theoretical results. A structure suitable for large frequency change is also discussed briefly.

We study the coupled spatio-temporal variations of the electron density and the electric field (electron plasma oscillations) in high-electron mobility transistors using the developed device model. The excitation of electron plasma oscillations in the terahertz range of frequencies might lead to the emission of terahertz radiation. In the framework of the model developed, we calculate the resonant plasma frequencies and find the conditions for the plasma oscillations self-excitation (plasma instability) We show that the transit-time effect in the high-electric field region near the drain edge of the channel of high-electron mobility transistors can cause the self-excitation of the plasma oscillations. It is shown that the self-excitation of plasma oscillations is possible when the ratio of the electron velocity in the high field region, ud, and the gate length, Lg, i.e., the inverse transit time are sufficiently large in comparison with the electron collision frequency in the gated channel, ν. The transit-time mechanism of plasma instability under consideration can superimpose on the Dyakonov-Shur mechanism predicted previously strongly affecting the conditions of the instability and, hence, terahertz emission. The instability mechanism under consideration might shed light on the origin of terahertz emission from high electron mobility transistors observed in recent experiments.

Plasma oscillations in nanometer field effect transistors are used for detection and generation of electromagnetic radiation of THz frequency. Following first observations of resonant detection in 150 nm gate length GaAs HEMT, we describe recent observations of room temperature detection in nanometer Si MOSFETs, resonant detection in GaN/AlGaN HEMTs and improvement of room temperature detection in GaAs HEMTs due to the drain current. Experiments on spectrally resolved THz emission are described that involve room and liquid helium temperature emission from nanometer GaInAs and GaN HEMTs.

The minimization problem of an L2-sensitivity measure subject to L2-norm dynamic-range scaling constraints is formulated for a class of two-dimensional (2-D) state-space digital filters. First, the problem is converted into an unconstrained optimization problem by using linear-algebraic techniques. Next, the unconstrained optimization problem is solved by applying an efficient quasi-Newton algorithm with closed-form formula for gradient evaluation. The coordinate transformation matrix obtained is then used to synthesize the optimal 2-D state-space filter structure that minimizes the L2-sensitivity measure subject to L2-norm dynamic-range scaling constraints. Finally, a numerical example is presented to illustrate the utility of the proposed technique.

Experimental investigations on detection of terahertz radiation are presented. We used plasma wave instability phenomenon in nanometer Silicon field effect transistor. A 30 nm gate length transistor was illuminated by THz radiation at room temperature. We observe a maximum signal near to the threshold voltage. This result clearly demonstrates the possibility of plasma wave THz operation of these nanometer scale devices. The response was attributed to a non resonant detection. We also demonstrate the possibility to observe a resonant detection on the same devices.

We consider oscillators consisting of a reactance circuit and a negative resistor. They may happen to have multi-mode oscillations around the anti-resonant frequencies of the reactance circuit. This kind of oscillators can be easily synthesized by setting the resonant and anti-resonant frequencies of the reactance circuits. However, it is not easy to analyze the oscillation phenomena, because they have multiple oscillations whose oscillations depend on the initial guesses. In this paper, we propose a Spice-oriented solution algorithm combining the harmonic balance method with Newton homotopy method that can find out the multiple solutions on the homotopy paths. In our analysis, the determining equations from the harmonic balance method are given by modified equivalent circuit models of "DC," "Cosine" and "Sine" circuits. The modified circuits can be solved by a simulator STC (solution curve tracing circuit), where the multiple oscillations are found by the transient analysis of Spice. Thus, we need not to derive the troublesome circuit equations, nor the mathematical transformations to get the determining equations. It makes the solution algorithms much simpler.

In this paper we focus on the decoding error of the Log-Likelihood Ratio Belief Propagation (LLR-BP) decoding algorithm caused by oscillation. The decoding error caused by the oscillation is dominant in high Eb/N0 region. Oscillation of the LLR of the extrinsic value in the bit node process (ex-LLR) is propagated to the other bits and affects the whole decoding. The Ordered Statistic Decoding (OSD) algorithm is known to improve the error rate performance of the LLR-BP decoding algorithm. The OSD algorithm is performed by deciding the reliability of each bit based on a posteriori probability. In this paper we propose two decoding algorithms based on two types of oscillations of LLR for LDPC codes. One is the oscillation-based OSD algorithm with deciding the reliability of each bit based on oscillation. The other is the oscillation-based LLR-BP decoding algorithm that modifies ex-LLR based on oscillation. In the oscillation-based LLR-BP decoding algorithm, when ex-LLR oscillates, then we reduce the magnitude of this ex-LLR to reduce the effects on the other bits. Both algorithms improve the decoding errors caused by oscillation. From the computer simulations, we show that paying attention to the oscillation, we can improve the error rate performance of the LLR-BP decoding algorithm.

Available Bit Rate (ABR) flow control is an effective measure in ATM network congestion control. In large scale and high-speed network, the simplicity of algorithm is crucial to optimize the switch performance. Although the binary flow control is very simple, the queue length and allowed cell rate (ACR) controlled by the standard EFCI algorithm oscillate with great amplitude, which has negative impact on the performance, so its applicability was doubted, and then the explicit rate feedback mechanism was introduced and explored. In this study, the model of binary flow control is built based on the fluid flow theory, and its correctness is validated by simulation experiments. The linear model describing the source end system how to regulate the cell rate is obtained through local linearization method. Then, we evaluate and analyze the standard EFCI algorithm using the describing function approach, which is well-developed in nonlinear control theory. The conclusion is that queue and ACR oscillations are caused by the inappropriate nonlinear control rule originated from intuition, but not intrinsic attribute of the binary flow control mechanism. The simulation experiments validate our analysis and conclusion. Finally, the new scheme about parameter settings is put forward to remedy the weakness existed in the standard EFCI switches without any change on the hardware architecture. The numerical results demonstrate that the new scheme is effective and fruitful.

Design approach to improving fmax of InP-based HBTs by combining lateral scaling (lithographic scaling) and vertical scaling (improving fT) is discussed. An HBT scaling model is formulated to provide means of analyzing the essential impact of scaling on fmax. The model was compared with measurements of single and double heterojunction bipolar transistors with different fT and various emitter sizes. While a high fmax of 313 GHz was achieved using submicron HBT with high fT, it was found that further improvement could have been obtained by reducing the emitter resistance, which has imposed considerable limit on lateral scaling.

When a feedback bridging fault occurs in a combinational circuit and it is activated, logical oscillation may occur in the circuit. In this paper, some electrical conditions are proposed to identify whether a feedback bridging fault occurs logical oscillation. Also, it is proposed how to estimate the oscillation frequency. They are based on piece linearlized models and do not require circuit simulation of large size of circuits. They are evaluated by some experiments. In the experiments, all of the feedback bridging faults occurring logical oscillation are identified. Also, oscillation frequencies larger than the ones obtained by SPICE simulation are derived by the proposed estimation method in the experiments. It promises us that the methods will be used for identifying such bridging faults and estimating the oscillation frequencies.

We propose an analysis method for Franz-Keldysh (FK) oscillations appearing in photoreflectance (PR) spectra of heterojunction device structures, which enables precise and simultaneous evaluation of the built-in electric field strength and band-gap energy. Samples for PR measurements were n+-GaAs/n-Al0.3 Ga0.7 As/i-GaAs heterostructures with different Al0.3Ga0.7As-layer thickness. We have found that the phase of the FK oscillations originating from the i-GaAs buffer layer depends on the Al0.3 Ga0.7 As-layer thickness. We have derived a calculation model for FK oscillations that includes the interference of probe light. From the comparison of the calculated spectra with the measured spectra, we conclude that mixing of the real and imaginary parts of a modulated dielectric function, which is caused by the probe-light interference, gives rise to the phase shift of the FK oscillations. Our FK-oscillation analysis method reduces ambiguity in the estimation of band-gap energy that is considerable in a conventional analysis.