A simplified distribution base resistance model (SDM) is proposed to identify each component of the base resistance and determine the dominant. This model divides the parasitic base resistance into one straight path and two surrounding paths. It is clarified that the link base resistance is dominant in a short emitter and the surrounding polysilicon base electrode resistance is dominant in a long emitter. In the SDM, the distance of the link base is reduced to half; with metal silicide as the extrinsic base electrode, the base resistance will be reduced to 75%.

The buried oxide nonintegrities, represented as the equivalent fixed oxide charge and interface trap densities at both the upper and lower interface of buried oxide, are evaluated for low-dose and high-dose SIMOX wafers, and their effects on device characteristics are investigated. The equivalent fixied oxide charge and trap densities at the lower interface, which are measured with buried oxide capacitors, are negligibly small in as-fabricated SIMOX wafers. This result enables us to make an analytical model of the parasitic drain/source-to-substrate capacitance in an SOI MOSFET, in which the effect of the depletion layer under the buried oxide is considered. The influence of thinner buried oxide and process-induced fixed oxide charge on the parasitic capacitance is explored with this model. The equivalent fixed oxide charge and trap densities at the upper interface are evaluated by the threshold voltage measurement in an SOI NMOSFET. The principle of this evaluation as well as the experimental technique are described in detail. The oxide charge and trap densities at the upper interface are higher than those at the lower interface for both SIMOX wafers. With a new model of the subthreshold slope based on a two-dimensional potential analysis the influence of the trap at the upper interface is discussed.

A simple method is presented to calculate the parasitic capacitance effect in the propagation delay of series-connected MOS (SCM) structures. This method divides SCM circuits into two parts and accurately calculates the contribution of each part to the difference from the delay without parasitic capacitances.

A novel isolation structure which has a buried insulator between polysilicon electrodes (BIPS) has been developed. The BIPS isolation employs the refilling CVD-oxides in openings between polysilicon electrodes by photoresist etchback process. Device characteristics and parasitic effects of BIPS isolation have been compared with that of LOCOS isolation. Using BIPS isolation, we can almost suppress the narrow-channel effects and achieve the deep submicron isolation. No degradation on the subthreshold decay of devices with BIPS isolation can be obtained. The use of BIPS isolation technology yields a DRAM cell of small area. The successful fabrication of deep submicron devices with BIPS isolation clearly demonstrates that this technology has superior ability to overcome the LOCOS isolation.

An omnidirectional microstrip antenna using a parasitic cylinder is presented. A rectangular patch is formed on a dielectric substrate and it's completely covered with an aluminum cylinder which is somewhat shorter than a half of free space wavelength. Under such configuration the aluminum cylinder works as a parasitic element. This antenna can provides uniform omnidirectional radiation patterns and a broad frequency bandwidth. In this paper an experimental method for designing such an element is described. Measured input impedance characteristics, current distribution around the surface of the cylinder and patterns are also shown. By properly adjusting the coupling intensity between the patch and the parasitic cylinder a broad bandwidth antenna element can be realized. Some methods to adjust the coupling intensity are shown. A wide bandwidth element up to 14% for VSWR1.5 is obtained. Arranging many patches lengthways on a substrate and placing metallic cylinders around each patches, we can realize a high-gain and broad bandwidth collinear antenna.

The paper presents the improvement of out new approach to optimize the process parameter variation, device heat and wire parasitics for analog LSI design by explicitly incorporating various performance estimations into objective functions for placement and routing. To minimize these objective functions, the placement by the simulated annealing method, and maze routing are effectively modified with the perfomance estimation. The improvement results in the excellent performance driven layout for the large size of analog LSIs.

This letter presents a technique to cancel the parasitic effects of operational amplifier (op amp) in active filter design. To minimize the effects, an op amp model considering the parasitics (i.e. both parasitic poles and zeros) is utilized. It is shown that undesirable factors in the transfer function due to the parasitics can be canceled well by predistorting the passive element values of the circuit. As an example, an active-R highpass filter is evaluated both theoretically and numerically. In this way, the proposed technique can be effectively incorporated into the design of active filters.

This paper describes a new approach towards the performance-driven layout for analog LSIs. Based on our approach, we developed an automatic performance-driven layout system LIBRA. The performance-driven layout has an advantage that numerical evaluations of performance requirements may exactly specify layout requirements so that a better layout result will be expected with regard to both the size and the performances. As the first step to the final goal, we only concern with the DC characteristics of analog circuits affected by the placement and routing. First of all, LIBRA performs the sensitivity analysis with respect to process parameters and wire parasitics, which are major causes for DC performance deviations of analog LSIs, so as to describe every perfomance deviation by its first order approximation. Based on the estimations of those performance deviations, LIBRA designs the placement of devices. The placement approach here is the simulated annealing method driven by their circuit performance specification. The routing of inter-cell wires is performed according to the priority of the larger total wire sensitivities in the net by the maze router. Then, the simple compaction eliminates the empty space as much as possible. After that, the power lines optimization is performed so as to minimize the ferformance deviations. Finally, an advantage of the performance improvement by our approach is demonstrated by showing a layout result of a practical bipolar circuit and its excellent performance evaluations.

Transmittance distribution along a horizontal line in LCDs addressed by amorphous silicon TFTs was investigated using measurements and calculations. Nonuniformity of the distribution, in which the transmittance increased with increasing distance from the left edge of the LCD, was observed in a 10 inch diagonal TFT-LCD. The cause of the nonuniformity was attributed to the decrease in voltage drop due to the gate source parasitic capacitance and the increase in gate voltage fall time due to large line resistance, based on the measurements of voltage drops in TFT test elements and calculations considering the decrease in voltage drop. The distribution could be improved by reducing the line resistance and parasitic capacitance in the actual LCD.