The parasitic capacitances induced in the spaces between an air-bridge interconnection and a drain pad (Cad), and between an air-bridge interconnection and a gate head (Cag) from a power CPW PHEMT are not negligible. In this paper, a modified equivalent circuit model for a CPW PHEMT and an improved CPW PHEMT for millimeter-wave applications are proposed. These were proved by measuring the fabricated CPW PHEMT and improved CPW PHEMT. These capacitances were confirmed by measuring the gate-source coupling using CPW PHEMT patterns without an active layer. From the measurements, the improved CPW PHEMT has the lowest coupling (loss) and the highest S21 gain among four different types tested at 60 GHz. And the improved CPW PHEMT is a feasible device which can be directly applied in millimeter-waves as a power device.

We proposed a push-pull output buffer that maintains the data transmission rate for lower supply voltages. It operates at an internal supply voltage (VDD) of 0.7-1.6 V and an interface supply voltage (VDDX) of 1.0-3.6 V. In low VDDX operation, the output buffer utilizes parasitic bipolar transistors instead of MOS transistors to maintain drivability. Furthermore forward body bias (FBB) control is provided for the level converter in low VDD operation. We fabricated a test chip with a standard 0.15 µm CMOS process. Measurement results indicate that the proposed output buffer achieves 200 Mbps operation at VDD of 0.7 V and VDDX of 1.0 V.

The problem of calculating parasitic capacitances between two interconnects is investigated dedicatedly for liquid crystal displays, with the main focus put on the approximate expressions of the capacitances caused at the intersection and the parallel running of two interconnects. To derive simple and accurate approximate expressions, the interconnects in these structures are divided into a few basic coupling regions in such a way that the electro-magnetic field in each region can be calculated by a 2-D capacitance model. Then the capacitance in such a region is represented by a simple expression adjusted to the results computed by an electro-magnetic field solver. The total capacitance obtained by summing the capacitances in all regions is evaluated in comparison with the one obtained by using a 3-D field solver, resulting in a relative error of less than 5%.

We present a new and efficient approach for extracting on-chip mutual inductances of VLSI interconnects by applying approximation formulae. The equations are based on the assumption of filaments or bars of finite width and zero thickness and are derived through Taylor's expansion of the exact formula for mutual inductance between filaments. Despite the assumption of uniform current density in each of the bars, the model is sufficiently accurate for the interconnections of current and future LSIs because the skin and proximity effects do not affect most wires. Expression of the equations in polynomial form provides a balance between accuracy and computational complexity. These equations are mapped according to the geometric structures for which they are most suitable in minimizing the runtime of inductance calculation while retaining the required accuracy. Within geometrical constraints, the wires are of arbitrary specification. Results of a comprehensive evaluation based on the ITRS-specified global wiring structure for 2003 shows that the inductance values were extracted by using the proposed approach, and they were within several percent of the values obtained by using commercial three-dimensional (3-D) field solvers. The efficiency of the proposed approach is also demonstrated by extraction from a real layout design that has 300-k interconnecting segments.

A three-mode switched-LNA has been developed using a 0.25 µm SiGe BiCMOS technology. The LNA features low noise figure (NF) performance, while achieving both low dissipation power and low distortion characteristics. The proposed MOSFET switch incorporating a newly developed switch circuit with a triple-well structure, which changes the LNA's mode, provides a parasitic capacitance of just 0.52 times that of a conventional MOSFET switch. This results in a significant NF improvement, by 0.16-0.33 dB, for the three-mode switched-LNA compared to a conventional LNA. Extensive studies of the MOSFET switch with regard to the structural parameters and the doping profiles are reported. Experimental results and the overall performance of a trial IC incorporating the three-mode switched-LNA are also given.

A formula-based approach for extracting the inductance of on-chip VLSI interconnections is presented. All of the formulae have been previously proposed and are well-known, but the degrees of accuracy they provide in this context have not previously been examined. The accuracy of the equations for a 0.1 µm technology node is evaluated through comparison of their results with those of 3-D field solvers. Comprehensive evaluation has proven that the maximum relative error of self- and mutual inductances as calculated by the formulae are less than 5% for parallel wires and less than 13% for angled wires, when wire width is limited to no more than 10 times the minimum. When applied to a realistic example with 43 wire segments, a program using the formula-based approach extracts values more than 60 times faster than a 3-D field solver.

This paper describes a three-port power divider with compensation networks for non-ideal isolation resistor. The compensation networks consist of two pairs of transmission lines and cancel out the parasitic reactance of the non-ideal isolation resistor. The design equations to provide perfect return loss and isolation at a center frequency are presented. The availability of the proposed power divider has been verified by the comparison between calculated and experimental results in the Ku-band.

This paper describes an electromagnetically coupled microstrip divider that provides high output port isolation and DC cutting. The device consists of a parasitic resonator placed above microstrip patch resonators, achieving tight coupling for both input and output ports. FDTD simulation and measurements reveal that the device has a high isolation between output ports. Equal and unequal 2-way and 3-way power dividers are presented in this paper.

Coupling between two slot antennas on an infinite ground plane and radiation patterns on a finite ground plane are calculated. We introduce a parasitic wire between slot antennas to reduce coupling. Two typical cases with a monopole or a half-loop are considered in this paper. Numerical results show that the reduction of 13.9 dB is obtained by adjusting a monopole height to about a quarter wavelength of the operating frequency. Also a properly adjusted parasitic half-loop reduces the coupling coefficient by 24 dB. Radiation patterns of the antennas on a 365 mm 465 mm ground plane at 1.5 GHz are calculated where the diffracted fields are taken into account. It is found that the parasitic elements little affect the antenna patterns around the +z-axis that is perpendicular to the ground plane although the reduction of coupling between slot antennas is obtained.

This paper proposes serially arranged two parasitic elements above a fed dipole to obtain broad bandwidth in resonant frequency of a parasitic element. The above antenna can be used in triple-bands with one feed point. Its design method using FDTD is also presented. Next, application of the triple-bands antenna is proposed for 3-sector base station antenna. Its characteristics of return loss and radiation patterns are indicated. Calculated values are in good agreement with measured ones.

We have quantitatively and systematically investigated the effect of parasitic inductance on rapid single flux quantum (RSFQ) circuits by numerical simulation. While a parasitic inductance in parallel to a junction has virtually no effect on the circuit performance, a parasitic inductance in series with a junction significantly reduces the operating margins and speeds of circuits that have been optimized with the assumption that no parasitic inductance exists. To improve the reduced margins and speeds we have re-optimized the circuits for operation with parasitic inductance. While the speeds are sufficiently improved by the re-optimization procedure, the margins do not reach those without the parasitics. This suggests that the parasitic inductance shrinks the operating regions of the circuits and improvement of the margins by changing only the values of the parameters is limited. For further improvement of the margins it is important to employ processes and layouts that minimize the series parasitic inductance.

In this paper, we propose an effective SOI yield engineering methodology by practical usage of 2D simulations. Process design for systematic yield of Fully-Depleted SOI MOSFET requires specific consideration of floating-body effects and parasitic channel leakage currents. The influence of varied SOI layer thickness to such phenomena is also complicated and substantial. Instead of time-consuming 3D simulators, 2D simulators are used to optimize the process considering these effects in acceptable turn around time. Our methodology is more effective in future scaled-down process with decreased SOI layer thickness.

We propose here a time-domain shooting algorithm for calculating the steady-state responses of nonlinear RF circuits containing parasitic elements that is based on both a modified Newton and a secant methods. Bipolar transistors and MOSFETs in ICs have small parasitic capacitors among their terminals. We can not neglect them because they will gives large effects to the shooting algorithm at the high frequency. Since our purpose is to develop a user friendly simulator, we mainly take into account the relatively large normal capacitors such as coupling and/or by-pass capacitors and so on, because the parasitic capacitors are usually smaller and contained in the device models. We have developed a very simple simulator only using the fundamental tools of SPICE, which can be applied to relatively large scale ICs, efficiently.

An advanced characterization method for sub-micron DRAM cell transistors has been proposed for the analysis of transistor test structures using memory cell patterns. When the actual memory cell layout is used as a test structure, the parasitic source and drain resistance of the test structure affected conventional transistor parameters such as threshold voltage. To solve this problem, reduced drain current measurement methods have been proposed to suppress the parasitic resistance voltage drop. In these measurements, two new transistor parameters, Vgoff and Vgsat, have been proposed which are related to off-leakage and full writing, respectively. These parameters are found to be good parameters for monitoring DRAM bit failures. A new threshold voltage measurement methodology has also been proposed for test structures with high parasitic resistance.

This paper presents a contact-less connector using proximity coupling through a parasitic element. For example, proximity coupling is used for interconnect of microstrip lines for DC-break structure. We also present a cross wiring structure using this interconnect.

Backfire quadrifilar helical antennas combined with parasitic loops are investigated in detail, focusing on clarifying the function of parasitic loops. First, the basic property is examined for the case of one parasitic loop, and it is found that the loop behaves as a director when the circumferential length of the loop is nearly 0. 9λ, and a reflector when the circumferential length of the loop is nearly 1. 2λ provided the distance between the parasitic loop and the top plane of helical antennas is approximately 0. 1λ, where λ is the wavelength. Next, the function of the parasitic loop is investigated by comparing the current distributions on the helices and the loop with those on a monofilar helix with a ground plane. It is found that the function of the parasitic loop is quite different from that of the ground plane. Then, the case of two parasitic loops is examined, and it is shown that the use of two parasitic loops is very effective and simple measures to control the radiation pattern and gain of the backfire quadrifilar helical antennas. Finally, for this type of antennas with two parasitic loops, an example of structural parameters suited to the use in satellite communications is presented.

Resonant properties of resistively shunted tunnel junctions dominate the high-frequency performance of Josephson array oscillators. To improve the operating frequency, we have developed resistively shunted Nb/AlOx/Nb tunnel junctions with a small parasitic inductance. The inductance was minimized by reducing the inductive length between the tunnel junction and the contact hole to be about 1µm. By fitting the measured I-V characteristics of the shunted tunnel junction to the simulated characteristics, we estimated the inductance to be about 105 fH. The analysis of resonant properties showed that the shunted tunnel junctions with the small parasitic inductance have a high-frequency performance up to the Nb gap frequency. Josephson array oscillators using 11 such junctions were designed and fabricated to operate at 650 GHz and 1 THz. Shapiro steps induced by Josephson oscillation were clearly observed up to 1 THz. By fitting the step heights to the simulated results, we estimated the output power of the Josephson oscillator delivered to the load resistor to be about 10 µW at 625 GHz and 50 nW at 1 THz.

The characteristics of circular polarization from a slot with a parasitic dipole are investigated analytically. It is derived that its phase is linearly dependent upon the angle of the dipole and is independent of that of slot. This interesting behavior is also confirmed by experiments.

In this paper we propose a comprehensive approach to physical design based on the constraint paradigm. Bounds on the most critical circuit parasitics are automatically generated to help designers and/or physical design tools meet a set of high-level specifications. The constraint generation engine is based on constrained optimization, where various parasitic effects on interconnect and devices are accounted for and dealt with in different manners according to their statistical behavior and their effect on performance.

The parasitic bipolar effect in a 200-V-class thin-film SOI power MOSFET fabricated using the silicon wafer direct bonding wafer was investigated by electrical measurement, two-dimensional process simulation, emission microscopy, and 2-dimensional thermal analysis. It degraded the breakdown voltage of the thin-film SOI power MOSFET and was caused by the increase in the sheet resistance of the body contact region. Photo emission analysis indicated that excess holes recombined in the n+-source region.