This paper presents an on-chip resonant supply noise canceller utilizing parasitic capacitance of sleep blocks. The test chip was fabricated in a 0.18 µm CMOS process and measurement results show 43.3% and 12.5% supply noise reduction on the abrupt supply voltage switching and the abrupt wake-up of a sleep block, respectively. The proposed method requires 1.5% area overhead for four 100 k-gate blocks, which is 7.1 X noise reduction efficient comparing with the conventional decap for the same power supply noise, while achieves 47% improvement of settling time. These results make fast switching of power mode possible for dynamic voltage scaling and power gating.

This paper proposes a channel capacity maximization method for Multiple-Input Multiple-Output (MIMO) antennas with parasitic elements. Reactive terminations are connected to the parasitic elements, and the reactance values are determined to achieve stochastically high channel capacity for the environment targeted. This method treats the S-parameter and propagation channel of the antenna, including the parasitic elements, as a combined circuit. The idea of the 'parasitic channel,' which is observed at the parasitic antenna, is introduced to simplify the optimization procedure. This method can significantly reduce the number of necessary measurements of the channel for designing the antenna. As a design example, a bidirectional Yagi-Uda array, which has two driven antennas at both ends of the linear array, is measured in an indoor environment. The resulting design offers enhanced channel capacity mainly due to its improved signal-to-noise ratio compared to the antenna without the parasitic antennas.

This paper evaluates impact of self-heating in wire interconnection on signal propagation delay in an upcoming 32 nm process technology, using practical physical parameters. This paper examines a 64-bit data transmission model as one of the most heating cases. Experimental results show that the maximum wire temperature increase due to the self-heating appears in the case where the ratio of interconnect delay becomes largest compared to the driver delay. However, even in the most significant case which induces the maximum temperature rise of 11.0, the corresponding increase in the wire resistance is 1.99% and the resulting delay increase is only 1.15%, as for the assumed 32 nm process. A part of the impact reduction of wire self-heating on timing comes from the size-effect of nano-scale wires.

Inductive effect becomes important for on-chip global interconnects, like the power/ground (P/G) grid. Because of the locality property of partial reluctance, the inverse of partial inductance, the window-based partial reluctance extraction has been applied for large-scale interconnect structures. In this paper, an efficient method of partial reluctance extraction is proposed for large-scale regular P/G grid structures. With a block reuse technique, the proposed method makes full use of the structural regularity of the P/G grid. Numerical results demonstrate the proposed method is able to efficiently handle a P/G grid with up to one hundred thousands wire segments. It is several tens times faster than the window-based method, while generating accurate frequency-dependent partial reluctance and resistance.

Power and ground planes on multilayer PCBs can effectively radiate electromagnetic fields excited by the IC simultaneous switching noise. The high frequency electromagnetic radiation is often calculated from the electric field along the edge of the PCB, which can be estimated with a cavity model using magnetic walls. The excitation of the cavity modes is related to the via current passing through the power bus planes at the interconnection between IC package and PCB. Usually the attention is focused on the differential-mode current of the package pins, but in the present paper it is shown that the common-mode current flowing out from package pins plays a very important role in the excitation of cavity modes, and its neglect implies a fatal underestimation of the electromagnetic radiation from the power bus planes in some circumstances. A second important contribute to the radiation is given by the common mode current on the pins, together with the current flowing on the PCB ground plane. With the proposed equivalent circuit, the effectiveness of decoupling inductors depending on their location and on the value of the parasitic capacitance is studied.

In this letter, a genetic programming method is used to synthesize filters. In order to improve the group delay characteristics, we propose a novel two-stage fitness function reflecting not only the frequency response but also the group delay characteristics of the evolved filters. We also deal with two practical design considerations, i.e., the filters include parasitic effects and are composed of elements with discrete values. The proposed method is applied to low-pass filter design cases. The experimental results show the method can effectively generate filters satisfying the design considerations and possessing improved group delay characteristics when compared with traditional filters.

In this paper, we have systematically investigated parasitic effects due to the gate and source-drain engineering in multi-gate transistors. The potential impact of high-K dielectrics on multi-gate MOSFETs (MuGFETs), such as FinFET, is evaluated through 2D and 3D device simulations over a wide range of proposed dielectric values. It is observed that introduction of high-K dielectrics will significantly degrade the short channel effects (SCEs), however a combination of oxide and high-K stack can effectively control this degradation. The degradation is mainly due to the increase in the internal fringe capacitance coupled with the decrease in gate-channel capacitance. From the circuit perspective, an optimum K value has been identified through mixed mode simulations. Further, as a part of this work, the importance of optimization of the shape of the spacer region is highlighted through full 3D simulations.

A new method is presented in order to improve the transient response of distributed amplifiers. The method is based on fitting the parameters of the distributed amplifier to those of a predesigned lowpass filter. Analytical expressions are derived to show the performance of the new structure. Three distributed amplifiers are designed based on the proposed method and it has been shown that the new method can significantly improve the transient response of the amplifier. It has been shown that the new method can improve the other characteristics of the distributed amplifier too. The effects of parasitic and lossy elements has also been considered and it has been shown that such effects doesn't violate the generality of the proposed theory.

In this paper, we propose an accurate and scalable S-parameter de-embedding method for RF/microwave on-wafer characterization of silicon MOSFETs. Based on cascade configurations, this method utilizes planar open, short, and thru standards to estimate the effects of surrounding parasitic networks on a MOS transistor. The bulk-shielded open and short standards are used to simulate and de-embed the probe-pad parasitics. The thru standard are used to extract the interconnect parameters for subtracting the interconnect parasitics in gate and drain terminals of the MOSFET. To further eliminate the parasitics of dangling leg in source terminal of the MOSFET, we also introduce the microwave and multi-port network analysis to accomplish the two-port-to-three-port transformation for S-parameters. The MOSFET and its corresponding de-embedding standards were fabricated in a standard CMOS process and characterized up to 40 GHz. The scalability of the open, short, and thru standards is demonstrated and the performance of the proposed de-embedding procedure is validated by comparison with several de-embedding techniques.

A de-embedding technique for the measurement of very small parasitic capacitances of package or small module interconnects is presented. At high frequencies small parasitic capacitances become important, and measurement probes can strongly affect measurement results. The present technique is based on additional measurements with only one tip of the probe touching one conductor, while the second tip is kept floating on the substrate. A necessary condition for its application is that the measured capacitance does not depend on the position of the floating probe tip. Measurements with inverted probe tip polarities are also used. In this way, the capacitances between probe tips and DUT can be estimated together with the parasitic capacitances of interest. Depending on the required accuracy, de-embedding of different orders have been introduced, which consider capacitance configurations of increasing complexity. The technique requires the solution of one or more systems of non-linear equations. In the present example the minimization of the norm of the residual of the system has been treated as a least squares problem, and has been solved numerically with MATLAB. The accuracy of the measurement can be also approximately estimated with the residual. As application example, a small module with power and ground planes has been considered. Two different probes have been used. Even though the stray capacitances of the probes are very different, the values of the extracted parasitic capacitances are in agreement with each other. The accuracy has been verified also with simulation results. To this purpose, a combination of known formulas from the literature, a 2D Finite Element Method (FEM) tool and a 3D Boundary Element Method (BEM) tool have been used. A high accuracy can be obtained, even when a strong capacitive coupling between probe ground and DUT is present. The technique can be applied also when only a subset of measurement results are available.

This paper describes a 1.2-V, 12-bit, 200-MSample/s current-steering CMOS digital-to-analog (D/A) converter for wireless-communication terminals. To our knowledge, the supply voltage of this converter is the lowest for high-speed applications. To overcome increasing device mismatch in low-voltage operation, we propose an H-shaped, 3-dimensional structure for reducing influence of voltage drops (IR drops) along power supplies. This technique relaxes mismatch requirements and allows use of small devices with small parasitics. By using this technique, a low-voltage, high-speed D/A converter was realized. The converter was implemented in a 90-nm CMOS technology. The modulator achieves the intrinsic accuracy of 12 bits and a spurious-free dynamic range (SFDR) above 55 dB over a 100-MHz bandwidth.

In this letter, we discuss the impact of intrinsic error in parasitic capacitance extraction programs which are commonly used in today's SoC design flows. Most of the extraction programs use pattern-matching methods which introduces an improvable error factor due to the pattern interpolation, and an intrinsically inescapable error factor from the difference of boundary conditions in the electro-magnetic field solver. Here, we study impact of the intrinsic error on timing and crosstalk noise estimation. We experimentally show that the resulting delay and noise estimation errors show a scatter which is normally distributed. Values of the standard deviations will help designers consider the intrinsic error compared with other variation factors.

This study is devoted to a half-wave dipole with a conductor plane at a distance much smaller than a quarter wavelength which we designate as an ultra low profile dipole (ULPD) antenna in this paper. The concerns of ULPD antenna are the feeding method and the impedance matching, because the input impedance usually tends to be lowered by the existence of a metallic structure in its proximity. In this paper, we propose a ULPD antenna with an excellent impedance matching and a coaxial feed built within the antenna structure so that the external matching and a balun are not required. A coaxial cable is used as a feed line and extended to be a half of a half wavelength dipole. The other half is made up of a parasitic element, which is connected to the outer conductor of the coaxial radiator. To make a matching, the outer conductor of the coaxial radiator is stripped off at a suitable length, and the total length of a dipole is considered for its resonance at a desired frequency of 2 GHz. The experiment has been conducted. The results show the return loss of -27 dB and the maximum gain of 9 dBi in the normal direction to the conductor plane. The computational results are also obtained, which agree well with the experimental results.

A design of a linearly-polarized non-resonant waveguide broad-wall transverse slot linear array with suppressed grating lobes is presented. Each unit element in the array consists of a transverse slot, an inductive post and a parasitic dipole-pair at a height of half of the free space wavelength. It is designed as an isolated unit without considering mutual coupling by using the Method of Moments (MoM) for radiation suppression in grating beam direction and reflection cancellation at the input. The elements thus designed are used in a travelling wave array environment. It is predicted that the reflection is less than -20 dB at 11.95 GHz while the grating lobes are suppressed by more than 15 dB. The design and the characteristics of the array are confirmed by measurements.

This paper proposes a new non-destructive methodology to estimate physical parameters for LSIs. In order to resolve the estimation accuracy degradation issue for low-k dielectric films, we employ a parallel-plate capacitance measurement and a wire resistance measurement in our non-destructive method. Due to (1) the response surface functions corresponding to the parallel-plate capacitance measurement and the wire resistance measurement and (2) the searching of the physical parameter values using our cost function and simulated annealing, the proposed method attains higher precision than that of the existing method. We demonstrate the effectiveness of our method by application to our 90 nm SoC process using low-k materials.

To cut down the sidelobe level of radiation pattern, a novel adaptive algorithm is proposed for electronic steering parasitic antenna. The composite objective function in this algorithm takes both directivity and sidelobe level of pattern into account, and the steepest gradient algorithm is selected to search the optimum value of reactive load. Simulations are carried out to validate the algorithm, simulated results show that the levels of sidelobe are both below -4 dB in different beamforming cases, and the front to back ratios are better than 10 dB.

This paper proposes the design to reduce the number of fed elements by replacing with parasitic elements in an array antenna. The study depends on the analysis of electromagnetic wave fields in consideration of the coupling between the half-wavelength dipoles. The case of 2 fed elements and 2 parasitic elements is considered as a unit cell to form the total array. After optimizing the element arrangement, the antenna gain can match that of the equivalent 4-fed element case. Feeding networks in a high power radiating system are analyzed in terms of the length and matching of feed lines, and the arrangement of amplifiers.

A new technique called the Dual Parasitic Beam (DPB) technique is proposed to suppress grating lobes in a rectangular waveguide broad wall transverse slot array. This technique involves an extra layer of parasitic strip dipoles that generate the DPB to suppress the grating lobes without opposing the main beam of the original slot linear array. A full wave EM analysis in Method of Moments (MoM) is conducted to compute the coupling excitation coefficients as well as the far field patterns of the slot and dipole currents. Analysis shows that a suitable dimension and arrangement of dipoles are needed to get a desired level of dipole excitations to meet the grating suppression condition. It is found that the grating lobes can be suppressed as much as 15 dB in the presence of the parasitic dipoles. Experiments are conducted to confirm the computed results.

This paper demonstrates an on-chip di/dt detector circuit. The di/dt detector circuit consists of a power supply line, an underlying spiral inductor and an amplifier. The mutual inductor induces a di/dt proportional voltage, and the amplifier amplifies and outputs the value. The measurement results show that the di/dt detector output and the voltage difference between a resistor have good agreement. The di/dt reduction by a decoupling capacitor is also measured using the di/dt detector.

There has recently been considerable interest in research on wearable non-grounded force display. However, there have been no developments for the communication of nonverbal information (ex. tennis and golf swing). We propose a small and lightweight wearable force display to present motion timing and direction. The display outputs a torque using rotational moment and mechanical brakes. We explain the principle of this device, and describe an actual measurement of the torque and torque sensitivity experiments.