This paper demonstrates that a 360° radio-frequency phase detector consisting of a combination of symmetrical mixers and 45° phase shifters with tunable devices can achieve a low phase-detection error over a wide frequency range. It is shown that the phase detection error does not depend on the voltage gain of the 45° phase shifter. This allows the usage of tunable devices as 45° phase shifters for a wide frequency range with low phase-detection errors. The fabricated phase detector having tunable low-pass filters as the tunable device demonstrates phase detection errors lower than 2.0° rms in the frequency range from 3.0 GHz to 10.5 GHz.

A 125MHz 64-phase delay-locked loop (DLL) is implemented for time recovery in a digital wire-line system. The architecture of the proposed DLL comprises a coarse-locking circuit added to a conventional DLL circuit, which consists of a delay line including a bias circuit, phase detector, charge pump, and loop filter. The proposed coarse-locking circuit reduces the locking time of the DLL and prevents harmonic locking, regardless of the duty cycle of the clock. In order to verify the performance of the proposed coarse-locking circuit, a 64-phase DLL with an operating frequency range of 40 to 200MHz is fabricated using a 0.18-µm 1-poly 6-metal CMOS process with a 1.8V supply. The measured rms and peak-to-peak jitter of the output clock are 3.07ps and 21.1ps, respectively. The DNL and INL of the 64-phase output clock are measured to be -0.338/+0.164 LSB and -0.464/+0.171 LSB, respectively, at an operating frequency of 125MHz. The area and power consumption of the implemented DLL are 0.3mm2 and 12.7mW, respectively.

Two phase detectors (PD) are proposed to minimize the phase offset and deadzone when used in DLL or PLL. With the shortest symmetrical racing paths from both inputs, the binary PD achieves fast latch operation and theoretical elimination of the setup time. In contrast to the conventional PDs whose offsets are around 10 ps with large sensitivity to sizing, the proposed binary PD shows an offset of less than 1 ps with a reduction of 30-percent delay time. The proposed latch-type binary phase detection is also expanded to form a linear PD by the addition of a reset-generating circuit.

A clock and data recovery (CDR) circuit using a new half-rate wide-range phase detection technique has been developed. Unlike the conventional three-state phase detectors, the proposed detector is applicable to the Non-Return-to-Zero (NRZ) data stream and also has low jitter and wide capture range characteristics. The CDR circuit was implemented in a 0.35-µm N-well CMOS technique. Experimental results demonstrate that it can achieve the peak-to-peak jitter of the recovered clock and the retimed data about 120 ps and 170 ps, respectively, while operating at the input data rate of 1 Gb/s. The total power dissipation of the CDR is 64.8 mW for the supply 3 V.

A CMOS DFE (decision feedback equalization) receiver with a clock-data skew compensation was implemented for the SSTL (stub-series terminated logic) SDRAM interface. The receiver consists of a 2 way interleaving DFE input buffer for ISI reduction and a X2 over-sampling phase detector for finding the optimum sampling clock position. The measurement results at 1.2 Gbps operation showed the increase of voltage margin by about 20% and the decrease of time jitter in the recovered sampling clock by about 40% by equalization in an SSTL channel with 2 pF 4 stub load. Active chip area and power consumption are 3001000 µm2 and 142 mW, respectively, with a 2.5 V, 0.25 µm CMOS process.

A new clock and data recovery circuit (CDR) is realized for the application of data communication systems requiring GHz-range clock signals. The high frequency jitter is one of major performance-limiting factors in CDR, particularly when NRZ data patterns are used. A novel phase detector is able to suppress this noise, and stable clock generation is achieved. Furthermore, optical characteristics for fast locking are achieved with the adaptive delay cell in the phase detector. The circuit is designed based on CMOS 0.25 µm fabrication process and its performance is verified by measurement results.

A simple phase detector reducing the pattern dependent jitter in clock recovery circuit is developed in this paper. The developed phase detector automatically aligns the recovered to clock in the center of the data eye, while producing no ripple to the control voltage in locked condition of the PLL based clock recovery circuit. The UP and DOWN signals are separately generated to align them in locked condition. Thus, no explicit transient waveforms do not exist at the output of the phase detector. The elimination of high frequency ripple improves the jitter characteristics of the clock recovery circuit. The delay unit used in our phase detector requires no accurate control of the delay time. This feature eliminates the use of DLL to generate the precise delay time, which reduce the power consumption and area of the phase detector. The simulation shows that the RMS timing jitter is reduced by more than four times when compared with the conventional scheme. The rms jitter is 32 ps for the proposed phase detector and 133 ps for the phase detector in conventional scheme. In conventional scheme, even when the lock is achieved, the phase detector produces a triwave transient on the control voltage of the VCO, which depends on the data pattern. In the proposed phase detector, no such transient waveforms do not exist. The proposed phase detector can be incorporated in high performance clock recovery circuit for data communication systems.

A multiphase low-jitter delay-locked loop (DLL) with harmonic-lock prevention, targeted at a gigabit parallel link interface, is delineated. A three-input four-state dynamic phase detector (PD) is proposed to obviate harmonic locking. Employing a low-jitter delay element and a new type of PD, the DLL is compact and feasible in its nature. The DLL is designed using a 0.35 µm 2P4M CMOS process with 3.3 V supply. Experimental results show that the circuit avoids false locking.

This paper describes a 1-GHz portable digital delay-locked loop (DLL) with 0.15-µm CMOS technology. There are three factors contributing to jitter in digital DLLs. One is supply-noise induced jitter, another is jitter caused by delay time resolution and phase step in the delay line, and the third is jitter caused by the sensitivity of the phase detector. In order to achieve a low jitter digital DLL, we have developed a master-slave architecture that achieves infinite phase capture ranges and low latency, a delay line that improves the delay time resolution, a phase step suppression technique and a dynamic phase detector with increased sensitivity. These techniques were used to fabricate a digital DLL with improved jitter performance. Measured results showed that the DLL successfully achieves 29-ps peak-to-peak jitter with a quiet supply and 0.2-ps/ mV supply sensitivity.

In this letter, we propose a polarity decision carrier recovery algorithm that is useful for carrier acquisition in high order QAM. The PD (Phase Detector) output and its variance characteristic are mathematically derived and the simulation results are presented. The proposed algorithm shows enhanced acquisition performance especially for large frequency offset.

In digital modulation for mobile radio telephone services frequency modulation with continuous phase with small modulation indices (MSK/GMSK) is sometimes used. Extension of the synchronization subsystems' pulling band in a coherent receiver and reducing synchronization delay is important for the mobile communication. At this moment there are only two possible synchronization schemes for the coherent MSK/GMSK receiver: Costas and de Buda's. This paper presents a new method (a possible alternative to both of them) where the frequency discriminator with decoupled carrier and bit synchronizing subsystem are combined to handle the task. For comparison, this paper also describes performances of the Costas carrier recovery scheme, which is widely employed for MSK/GMSK coherent demodulation. Discrimination and fluctuation characteristics for frequency, phase, and symbol delay synchronization subsystems are shown and the BER degradation from the conventional Costas scheme is calculated. This paper demonstrates with simulation results that the proposed scheme improves RF carrier acquisition performances, and at the same time, for large signal-to-noise ratios (SNR's) provides similar or better tracking performances than the Costas one. While limited to higher SNR ratios, the proposed synchronization scheme is suitable for many applications and can be implemented with simpler circuitry, well suited to integrated circuit implementation.

The lock-up time of a PLL frequency synthesizer mainly depends on the total loop gain. Since the gain of the conventional phase detector is constant, it is difficult to improve the lock-up time by the phase detector. In this paper, we reconsider the operation of the phase detector and propose the PLL frequency synthesizer with multi-phase detector in which the gain of phase detector is increased by using four stage phase detectors and charge pumps. Then, a higher speed lock-up time and good spurious characteristics can be achieved.

This letter demonstrates that, under certain condition, the harmonic content of a rectangular pulse train is reduced by a considerable extent in the presence of another equal frequency pulse train of opposite polarity. The condition for maximum harmonic rejection is derived. It is also shown that this technique can, very effectively, be applied to reduce the harmonic content of a sequential phase detector (PD) output. This letter also presents the experimental performance of a sequential PD, incorporating this technique, in a single-loop synthesizer.

In order to investigate the jitter characteristics of PLLs for practical applications, we have developed a computer simulation program of PLL, which can deal with arbitrary patterns both of data and jitters, as well as a conceivable nonlinearity of the circuit performance. We used a time-domain method, namely, we solved the state equation of a charge pump type PLL with a constant time step. The jitter transfer characteristics of a conventional PLL were calculated for periodic input data patterns with sinusoidal jitters. The result agreed fairly well with the corresponding experiments. And we have revealed that an ordinary PD (Phase Detector), which detects the phase difference between input and VCO signals at only rising edges, shows the folded jitter transfer characteristics at the half of the equivalent frequency of the input signal. This folded jitter characteristics increases the total jitter for long successive '1' or '0' data patterns, because of their low equivalent sampling frequency, and might increase the jitter even for the random data patterns. Based on simulation results, we devised an improved phase detector for PLL having a low jitter characteristics. And we also applied the simulation to an FDD (Frequency Difference Detector) type fast pull-in PLL which we have proposed recently, and obtained that the jitter of it was smaller than that of a conventional PLL by 25% for PRBS (pseudo random bit sequence) NRZ code.