Hardware/software partitioning is one of the key processes in a hardware/software cosynthesis system for digital signal processor cores. In hardware/software partitioning, area and delay estimation of a processor core plays an important role since the hardware/software partitioning process must determine which part of a processor core should be realized by hardware units and which part should be realized by a sequence of instructions based on execution time of an input application program and area of a synthesized processor core. This paper proposes area and delay estimation equations for digital signal processor cores. For area estimation, we show that total area for a processor core can be derived from the sum of area for a processor kernel and area for additional hardware units. Area for a processor kernel can be mainly obtained by minimum area for a processor kernel and overheads for adding hardware units and registers. Area for a hardware unit can be mainly obtained by its type and operation bit width. For delay estimation, we show that critical path delay for a processor core can be derived from the delay of a hardware unit which is on the critical path in the processor core. Experimental results demonstrate that errors of area estimation are less than 2% and errors of delay estimation are less than 2 ns when comparing estimated area and delay with logic-synthesized area and delay.

In this paper, we propose a unified high-radix division algorithm for high-speed signal and data processing applications, and present the design and evaluation of high-radix parallel dividers based on the proposed algorithm. By prescaling the input operands and converting some significant digits of a partial remainder into non-redundant representation, the quotient digit can be obtained directly from the partial remainder without using quotient digit selection tables. Performance evaluation shows that the proposed radix-4 and radix-8 divider architectures achieve faster computation with the same level of hardware complexity than the binary counterparts. We also show an experimental fabrication of a radix-4 divider chip in 0.35 µm CMOS technology.

In this paper, we present an RTL design-space exploration method for high-level applications. We formulate the RTL design-space exploration into a performance-driven module selection problem. We devise a dynamic-programming algorithm to solve the problem. We present an exploration flow by integrating commercial synthesis and layout tools with our proposed method. Experimental results have demonstrated that generating AT-curve for all modules is the most time consuming task in the design-space exploration process. Using the proposed 3-point AT projection approach, our method can achieve on an average of 80% speed-up in run time and 90% accuracy in design estimation.

An automated analog circuit synthesis based on reuse of topological features of 'prototype circuits' is proposed. The prototype circuits are designed by humans and suggested to the synthesis system as hints of configurations of new analog circuits to be synthesized by the system. The connections of elements in analog circuits are not generally systematic, but they would have some similarities to a circuit which has similar behaviors or functionalities. In the proposed process, the information on circuit connections is stored as sub-circuits extracted from the prototype circuits. And then, genetic algorithm is used to search for an optimum combination of the sub-circuits that achieves the desired electronic specifications. The combinations of sub-circuits are performed with a novel technique where the terminals of the sub-circuits are shared. The capabilities of the proposed method are demonstrated through an example of the synthesis.

This letter proposes a hardware/software partitioning algorithm for digital signal processor cores with two register files. Given a compiled assembly code and a timing constraint of execution time, the proposed algorithm generates a processor core configuration with a new assembly code running on the generated processor core. The proposed algorithm considers two register files and determines the number of registers in each of register files. Moreover the algorithm considers two or more types of functional units for each arithmetic or logical operation and assigns functional units with small area to a processor core without causing performance penalty. A generated processor core will have small area compared with processor cores which have a single register file or those which consider only one type of functional units for each operation. The experimental results demonstrate the effectiveness and efficiency of the proposed algorithm.

This paper presents an automatic synthesis method of active analog circuits that uses evolutionary search and employs some topological features of analog integrated circuits. Our system firstly generates a set of circuits at random, and then evolves their topologies and device sizing to fit an environment which is formed by the fitness function translated from the electrical specifications of the circuit. Therefore expert knowledge about circuit topologies and sizing are not needed. The capability of this method is demonstrated through experiments of automatic synthesis of CMOS operational amplifiers.

In 2000, Wang et al. proposed a new (t,n) threshold signature scheme with (k,l) threshold shared verification. Meanwhile, integrating the idea of message recovery, they also proposed a (t,n) threshold authenticated encryption scheme with (k,l) threshold shared verification. However, this article will show that both proposed schemes are insecure, because any malicious attacker can obtain the group secret keys from two valid threshold signatures. Thus, the attacker may solely forge or verify a threshold signature. An improvement to overcome the attacks is proposed.

Simulation based education and training, especially wargame simulations, are being used widely in the field of defense modeling and in simulation communities. In order to efficiently train students and trainees, the wargame simulations must have both high performance and high fidelity. In this paper, we discuss design and implementation issues for a prototype of a parallel and distributed wargame simulation system. This wargame simulation system is based on High Level Architecture (HLA) and employs some optimization to achieve both high performance and high fidelity in the simulation system. The results show that the proposed optimization method is effective when optimization is applied to 93.5% or less of the moving objects (PFs) within the range of detection (RofD) of both the red and blue teams. Specifically, when each team has 1000 PFs we found that if the percentage of PFs within RofD is less than 50% for both teams, our method is over two times better than for the situation where there is no optimization.

It is necessary condition for digital watermarking method for embedding memos or index data into digital photograph and so on that anyone can extract embedded data without specific keys or secret information. In this paper, we propose a data hiding technique for embedding index data into color images using wavelet transform. The proposed method keeps image quality and robustness against JPEG compression and general image processing using quantitative relation of wavelet coefficients.

Multisignature scheme realizes that plural users generate the signature on a message, and that the signature is verified. Various studies on multisignature have been proposed. They are classified into two types: RSA-based multisignature, and discrete logarithm problem (DLP) based multisignature, all of which assume that a message is fixed beforehand. In a sense, these schemes do not have a feature of message flexibility. Furthermore all schemes which satisfy with order verifiability designate order of signers beforehand. Therefore these protocols have a feature of order verifiability but not order flexibility. For a practical purpose of circulating messages soundly through Internet, a multisignature scheme with message flexibility, order flexibility and order verifiability should be required. However, unfortunately, all previous multisignature do not realize these features. In this paper, we propose a general model of multisignature schemes with flexibility and verifiability. We also present two practical schemes based on DLP based message recover signature and RSA signature, respectively.

We present a design strategy to reduce power demands in application-specific, heterogeneous multiprocessor systems with interdependent subtasks. This power reduction scheme can be used with a randomised search such as a genetic algorithm where multiple trial solutions are tested. The scheme is applied to each trial solution after allocation and scheduling have been performed. Power savings are achieved by equally expanding each processor's execution time with a corresponding reduction in their respective operating voltage. Lowest cost solutions achieve average reductions of 24% while minimum power solutions average 58%.

Several subband array methods have been proposed as useful means to perform joint spatio-temporal equalization in digital mobile communications. These methods can be applied to mitigate problems caused by the inter-symbol interference (ISI) and co-channel interference (CCI). The subband array methods proposed so far can be classified into two major schemes: (1) a centralized feedback scheme and (2) a localized feedback scheme. In this paper, we propose subband arrays with partial feedback scheme, which generalize the above two feedback schemes. The main contribution of this paper is to derive the steady-state mean square error (MSE) performance of subband arrays implementing these three different feedback schemes. Unlike the centralized feedback scheme which can be designed to provide the optimum equalization performance, the subband arrays with localized and partial feedback schemes are in general suboptimal. The performance of these two suboptimal feedback schemes depends on the channel characteristics, the filter banks employed, and the number of subbands.

The effect of Unbalanced-Magnetic-Pull (UMP) on vibration and run-outs has become stringent in the design for high performance HDD spindle motors. In this paper, reducing the UMP and also minimizing its variability for an 8-pole 9-slot spindle motor to achieve robustness in the performance is described and illustrated using novel robust design methods. A screening experiment identifies the key design parameters. Using Design of experiment (DOE) and Analysis of Variance (ANOVA), the parameter design reduces the amplitude of UMP and minimizes its variability by product parameter optimization. The tolerance design improves the quality by tightening tolerances on product or process parameters to reduce the performance variation. The optimal design process includes considerations of manufacturing and process noises, such as manufacturing tolerances for the slot opening and variation of the rotor magnet magnetization distribution due to the magnetization fixture and process. The optimal design procedure is briefly introduced and the results are presented.

To generalize characteristics of a received signal level distribution from narrow- to wide-bands in a mobile radio channel, a new propagation parameter called equivalent received bandwidth (2ΔfΔLmax) has been proposed. The distributions are discussed mainly with computer simulation results. The simulation results shows the level distribution depends on 2ΔfΔLmax and power ratio a of direct to indirect waves, and the value of 2ΔfΔLmax classifies the radio channel as narrow- or wide-bands transmission. To confirm these simulated results, a field test was performed with a 3.35 GHz radio wave. This paper describes that the field test demonstrated the simulation results. It is concluded that the equation representing received signal level in the computer simulation is valid. And the fading depth depends directly on 2ΔfΔLmax, and the 2ΔfΔLmax is effective for generalizing the received signal level distribution. Furthermore, a method for calculating the power ratio was found to be better for a peak level model.

An optically controlled beamforming technique is a very effect procedure for phased array antenna control. We have built a Fourier optical processing beamforming network. In the optical processor, we use optical waveguide arrays and a GRIN micro lens in order to reduce the size and weight of the processor, optical coupling losses, mechanical destabilization, and optical alignment difficulties. This paper describes the characteristics of a one-dimensional Fourier optical processor, and shows the configurations of both its transmitting and receiving modes, which we have constructed. We demonstrate multiple signal generation, and beam steering for transmission in the X-band. Furthermore, we configure the beamformer for reception using the phase information of local signals form the optical processor. We additionally demonstrate the beam steering of the received X-band RF signal. Experimental results confirm the feasibility of the Fourier optical processing beamforming network.

Analysis of a novel folded loop antenna for handset is described along with the advanced design concept for handset antennas. The design concept shown in this paper meets the foremost requirement for handset antennas such as (1) small size and yet (2) has capability of mitigating degradation of antenna performance due to the body effect, and (3) of reducing SAR value in the human head at the handset talk position, in addition to the indispensable requirements for handset antennas such as (4) low profile, and (5) light weight. The technology applied is to make this antenna (a) an integrated structure, which is a typical application of the fundamental concept of making antennas small and (b) a balanced structure which has been proved to be very effective to satisfy the requirements (2) and (3). The antenna is essentially a two-wire transmission line, folded at about a quarter-wavelength to form a half-wave folded dipole, and yet appears to be a loop of one-wavelength. It does not have really a balanced structure, as is fed with an unbalanced line; however, the antenna structure itself can eliminate the unbalanced current flow on the feed line as in the balanced antenna system. Both theoretical and experimental analyses have been shown and the usefulness of the antenna is discussed. This paper may suggest the advanced technology and design concept that will be applied to the development of handset antennas toward the future.

This work presents a novel channel assignment scheme for low earth-orbit (LEO) satellite-based mobile communication systems, in which any newly generated call will first be assigned an optimum channel and will no longer be reassigned even when it crosses the boundary of the cell. Thus, the compact reuse distance can be maintained and no handoff failure will occur owing to channel unavailability. Furthermore, a high quality service which guarantees successful handoff processes can be provided. The performance of the proposed strategy is analyzed and compared with the performances of the fixed channel assignment (FCA) scheme and dynamic channel assignment schemes.

Broadband fixed wireless access (FWA) systems offer significantly higher bit rates than current cellular systems to which adaptive arrays are partly applied. Digital beam forming is being eagerly explored on account of its flexibility, but it will be difficult to apply to the high-speed systems, because its digital signal processing requires huge resources and power consumption. Conventional phased arrays, on the other hand, utilize phase shifters through RF or IF signal lines, but the phase shifters are usually both bulky and expensive. The authors propose an adaptive array steered by IF local signal phase shifters in this paper. The phase shift and the frequency shift of the signal from each antenna element can be simultaneously accomplished at the down conversion stage by the phase-controlled local signal. A prototype receiver operated in the K-band with the proposed configuration and its beam pattern measurement results are also described.

An analytic equation was derived for the time jitter of digital NRZ signals due to inter-symbol interference in the PCB transmission lines loaded by DRAM chips which are located in uniform spacing. The inter-symbol interference is caused by a low-pass filtering effect of the loaded transmission line. Good agreements were observed between the equation and measurements with an average error of 17.5%.

The formulation of the process of analog system design has been done on the basis of the control theory application. This approach generalizes the design process and produces different design trajectories inside the same optimization procedure. The problem of the optimal design algorithm construction is defined as the minimal-time problem of the control theory. The main equations for the proposed design methodology were elaborated. These equations include the special control functions that are introduced artificially to generalize the design problem. Optimal dependencies of the control functions give the possibility to reduce the total computer design time. This idea was tested with different optimization algorithms of the design process. Numerical results of some simple electronic circuit design demonstrate the efficiency of the proposed approach. These examples show that the traditional design strategy is not time-optimal and the potential computer time gain of the optimal design strategy increases when the size and complexity of the system increase.