The explicit formula for the coefficients of maximally linear digital differentiators is derived by the use of Taylor series. A modification in the formula is proposed to extend the effective passband of the differentiator with the same number of coefficients.

This paper discusses factorization of bent function type complex Hadamard matrices of order pn with a prime p. It is shown that any bent function type complex Hadamard matrix has symmetrical factorization, which can be expressed by the product of n matrices of order pn with pn+1 non-zero elements, a matrix of order pn with pn non-zero ones, and the n matrices, at most. As its application, a correlator for M-ary spread spectrum communications is successfully given, which can be simply constructed by the same circuits with reduced multiplicators, before and behind.

As many research works are based on some previous results, my paper, namely The Integrated Scheduling and Allocation of High-Level Test Synthesis, makes use of some techniques by T. Kim. However, I did not state explicitly that some parts of my work are based on Kim's approach although I have referred to his paper. I would like to express my deep apology to Kim for not having emphasized Kim's contribution to my work. But my intention was not to steal Kim's ideas. I would like to emphasize the following difference.

Image coding with vector quantization (VQ) reveals several defects which include edge degradation and high encoding complexity. This paper presents an edge-preserving coding system based on VQ to overcome these defects. A signal processing unit first classifies image blocks into low-activity or high-activity class. A high-activity block is then decomposed into a smoothing factor, a bit-plane and a smoother (lower variance) block. These outputs can be more efficiently encoded by VQ with lower distortion. A set of visual patterns is used to encode the bit-planes by binary vector quantization. We also develop a modified search-order coding to further reduce the redundancy of quantization indexes. Simulation results show that the proposed algorithm achieves much better perceptual quality with higher compression ratio and significant lower computational complexity, as compared to the direct VQ.

Guided Scrambling (GS) is used for control of the runlength within code blocks, such as d or k, as well as for DC component suppression. A code designed by the GS technique, called a weakly constrained code, does not strictly guarantee the imposed k-constraint, but rather generates code blocks that violate the prescribed constraint with very low probability. In this case, the code rate and efficiency become very high, compared with typical RLL codes using a small constrained length. In this paper, weakly constrained codes based on the convolutional GS and GF-addition GS generate the weakly k-constraint sequences. The probability that a code block violates the k-constraint is measured. To show the superior performance of the GS, the occurrence probability of each runlength is also investigated and compared with the 24/25(0, 8) block code which has a high code rate and adheres to channel constraints. We also compare it with the runlength distribution of a maxentropic RLL sequence and show that the statistical property of the GS-encoded sequences is similar to that of the maxentropic RLL sequence on runlength distribution.

This paper proposes a new vector error measurement scheme for orthogonal frequency division multiplexing (OFDM) systems that is used to define transmit modulation accuracy. The transmit modulation accuracy is defined to guarantee inter-operability among wireless terminals. In OFDM systems, the transmit modulation accuracy measured by the conventional vector error measurement scheme can not guarantee inter-operability due to the effect of phase noise. To overcome this problem, the proposed vector error measurement scheme utilizes pilot signals in multiple OFDM symbols to compensate the phase rotation caused by the phase noise. Computer simulation results show that the vector error measured by the proposed scheme uniquely corresponds to the C/N degradation in packet error rate even if phase noise exists in the OFDM signals. This means that the proposed vector error measurement scheme makes it possible to define the transmit modulation accuracy and so guarantee inter-operability among wireless terminals.

This paper proposes a phase assignment algorithm "Silent Wave Algorithm (SWA)" for real-time MPEG traffic in ATM networks. Our algorithm decides when a new MPEG source should begin to transmit based on its notification parameters and traffic measurement of ongoing connections. Simulation results show that it is hard to accommodate MPEG traffic effectively without any control of phase assignment. On the other hand, the SWA can provide better QOS and improve the network utilization.

I would like to draw the attention of the editorial board of IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences and its readers to a recent paper, Tianruo Yang, "The integrated scheduling and allocation of high-level test synthesis," vol. E82-A, no. 1, January 1999, pp. 145-158. (Here we call this paper the Yang's paper. ) Yang did not give the correct information about the originality of the paper. I will point out that the writings (and the idea accordingly) of section 6 of Yang's paper came from papers [1] and [2].

This paper presents a quadriphase sequence pair, whose aperiodic auto-correlation functions for non-zero shifts and cross-one for any shift take pure imaginary values. Functions for pairs of length 2n are formulated, which map the vector space of order n over GF(2) to Z4. It is shown that they are bent for any n, such that their Fourier transforms take all the unit magnitude.

This paper proposes a novel spread spectrum (SS) modem for random access satellite communication systems that employs digital matched filters. The proposed modem employs a parallel structure to ensure detection of packet arrival. Code timing detection with a combination of a coarse detector and a fractional error detector reduces the sampling rate while maintaining the BER performance. An in-symbol pilot multiplexing scheme is also proposed for fast and stable carrier synchronization with a simple hardware. A performance evaluation shows that the proposed modem achieves the UW miss-detection probability of 10-4 at the Eb/No of 0 dB. The overall BER performance achieved in experiments well agrees simulation.

Linear signal analysis (LSA) is the conventional method of estimating the playback voltage and pulse width in linearly operating shielded GMR heads. To improve the accuracy of LSA, a new, highly precise LSA which includes the effect of the magnetization distribution in the medium and inhomogeneous biasing by domain control magnets, was developed. Utilizing this new LSA to calculate the playback waveforms, the calculated peak voltage and pulse width were compared with the experimental values and agreement within 10% was obtained. As the result of estimation using the new LSA, it is considered that the use of a vertical-type spin-valve head will make it possible to achieve a recording areal density of 40 Gb/in2.

This paper proposes a hardware/software cosynthesis system for digital signal processor cores and a hardware/software partitioning algorithm which is one of the key issues for the system. The target processor has a VLIW-type core which can be composed of a processor kernel, multiple data memory buses (X-bus and Y-bus), hardware loop units, addressing units, and multiple functional units. The processor kernel includes five pipeline stages (RISC-type kernel) or three pipeline stages (DSP-type kernel). Given an application program written in the C language and a set of application data, the system synthesizes a processor core by selecting an appropriate kernel (RISC-type or DSP-type kernel) and required hardware units according to the application program/data and the hardware costs. The system also generates the object code for the application program and a software environment (compiler and simulator) for the processor core. The experimental results demonstrate that the system synthesizes processor cores effectively according to the features of an application program and the synthesized processor cores execute most application programs with the minimum number of clock cycles compared with several existing processors.

This paper describes a novel layout optimization technique using electromagnetic (EM) simulation. Simple equivalent circuits fitted to EM simulation results are employed in this method, to present a modification guide for a layout pattern. Fitting errors are also investigated with some layout patterns in order to clarify the applicable range of the method, because the errors restrict the range. The method has been successfully adopted to an X-band low noise MMIC amplifier (LNA). The layout pattern of the amplifier was optimized in only two days and the amplifier has achieved target performances--a 35 dB gain and a 1.7 dB noise figure--in one development cycle. The effective chip area has been miniaturized to 4.8 mm2. The area could be smaller than 70% in comparison with a conventional layout MMIC.

A procedure for radar target discrimination is presented in this paper. The scheme includes an enhancement of late-time noisy scattering data based on a proposed signal processing algorithm and a decision procedure using previously known resonance annihilation filters. The signal processing stage is specifically adapted to scattering signals and makes use of the results of the singularity expansion method. It is based on a signal reconstruction using the SVD of a data matrix with a suitable choice of the number of singular vectors employed. To justify the inclusion of this stage, this procedure is shown to maintain the signal characteristics necessary to identify the scattered response. Simulation results clearly reveal a significant improvement due to the inclusion of the proposed stage. This improvement becomes especially important when the noise level is high or the targets to be discriminated (five regular polygonal loops) have a similar geometry.

A parallel detailed router based on the area division is one of important tools to overcome the increase of CPU time required for routing of a very large multilayer SOG. In order to conduct routing in each divided area independently, fictitious terminals are introduced on the border of each divided area, and routes connected to the fictitious terminals are concatenated to complete the final detailed routes. In this paper, we consider a problem how to position such fictitious terminals on borders, so as to make each detailed routing in a divided area easy. We formulate this problem as a minimum cost assignment problem, and propose an iterative improvement algorithm. We also give some experimental results which indicate the effectiveness of the algorithm.

In this paper, a novel application specific power optimization technique utilizing small instruction ROM which is placed between an instruction cache or a main program memory and CPU core is proposed. Our optimization technique targets embedded systems which assume the following: (i) instruction memories are organized by two on-chip memories, a main program memory and a subprogram memory, (ii) these two memories can be independently powered-up or powered-down by a special instruction of a core processor, and (iii) a compiler optimizes an allocation of object code into these two memories so as to minimize average of read energy consumption. In many application programs, only a few basic blocks are frequently executed. Therefore, allocating these frequently executed basic blocks into low power subprogram memory leads significant energy reduction. Our experiments with actual ROM (Read Only Memory) modules created with 0.5 µm CMOS process technology, and MPEG2 codec program demonstrate significant energy reductions up to more than 50% at best case over the previous approach that applies only divided bit and word lines structure.

In the hardware synthesis methods with high level languages such as C language, optimization quality of the compilers has a great influence on the area and speed of the synthesized circuits. Among hardware-oriented optimization methods required in such compilers, minimization of the bit length of the data-paths is one of the most important issues. In this paper, we propose an estimation algorithm of the necessary bit length of variables for this aim. The algorithm analyzes the control/data-flow graph translated from C programs and decides the bit length of each variable. On several experiments, the bit length of variables can be reduced by half with respect to the declared length. This method is effective not only for reducing the circuit area but also for reducing the delay of the operation units such as adders.

This paper describes an IC implementation of current-mode chaotic neuron circuit for the chaotic neural network. The chaotic neuron circuit which composes of a first generation switched-current integrator and a conventional current amplifier is fabricated in a standard 0.8 µ m CMOS technology. Experimental results of the chaotic neuron circuit reproduce the dynamical behavior of the chaotic neuron model.

This paper presents an algorithm for the scan-chain optimization problem in multiple-scan design methodology. The proposed algorithm, which consists of four phases, first determines pairs of scan-in and scan-out pins (Phase 1), and then assigns flip-flops to scan-paths by using a graph theoretical method (Phase 2). Next the algorithm decides connection-order of flip-flops in each scan-path by using TSP (Traveling Salesman Problem) heuristics (Phase 3), and finally exchanges flip-flops among scan-paths in order to reduce total scan-path length (Phase 4). Experiments using actual design data show that, for ten scan-paths, our algorithm achieved a 90% reduction in scan-test time at the expense of a 7% total scan-path length increase as compared with the length of a single optimized scan-path. Also, our algorithm produced less total scan-path length than other three possible algorithms in a reasonable computing time.

Weighted summation (W-SUM) operation of multi-input signals plays an important role in signal processing, image compression and communication systems. Conventional digital LSI implementation for the massive high-speed W-SUM operations usually consumes a lot of power, and the power dissipation linearly increases with the operational frequencies. Analog or digital-analog mixed technology may provide a solution to this problem, but the large scale integration for analog circuits especially for digital-analog mixed circuits faces some difficulties in terms of circuit design, mixed-simulation, physical layout and anti-noises. To practically integrate large scale analog or digital-analog mixed circuits, the simplicity of the analog circuits are usually required. In this paper, we present a solution to realize the parallel W-SUM operations of multi-input analog signals based on our developed digital-controlled analog operational circuits. The major features of the proposed circuits include the simplicity in the circuitry architecture and the advantage in the dissipation power, which make it easy to be designed and to be integrated in large scale. To improve the design efficiency, a Top-Down design approach for mixed LSI implementation is proposed. The proposed W-SUM circuits and the Top-Down design approach have been practically used in the LSI implementation for a series of programmable finite impulse response (FIR) filters and matched filters applied in adaptive signal processing and the mobile communication systems based on the wideband code division multiple access (W-CDMA) technology.