Recent DSP applications have many significant issues such as higher system performance, lower power consumption, higher design flexibility, faster time-to-market, and so on. Neither a conventional ASIC nor a conventional DSP can necessarily satisfy all the requirements at once nowadays. Therefore, an alternate for DSP applications will be needed to complement the drawbacks of ASICs and DSPs. This paper introduces a new computing paradigm called configurable computing or reconfigurable computing, which has more potential in terms of performance and flexibility. Conventional silicon platforms will not satisfy the conflicting demands of standard products and customization. However, silicon platforms such as FPGAs for configurable or reconfigurable computing are standardized in manufacturing but customized in application. This paper also presents a brief survey of the existing silicon platforms that support configuration or reconfiguration in the application domain of digital signal processing such as image processing, communication processing, audio and speech processing. Finally, we show some promising reconfigurable architectures for the digital signal processing and discuss the future of reconfigurable computing.

A new method is proposed for determining the parasitic extrinsic resistances of MESFETs and HEMTs from the measured S-parameters under active bias. The proposed method is based on the fact that the difference between drain resistance (Rd) and source resistance (Rs) can be found from the measured S-parameters under zero bias condition. It is possible to define the new internal device including intrinsic device and three extrinsic resistances by eliminating the parasitic imaginary terms. Three resistances can be calculated easily via the presented explicit three equations, which are induced from the fact that 1) the real parts of Yint,11 and Yint,12 of intrinsic Y-parameters are very small or almost zero, 2) the transformation relations between S-, Z-, and Y-matrices. The modelled S-parameters calculated by the obtained resistances and all the other equivalent circuit parameters are in good agreement with the measured S-parameters up to 40 GHz.

In this paper, we propose an improved network-flow based multi-way circuit partitioning algorithm whose objective is to minimize the number of sub-circuits. It iteratively extracts a size-maximal feasible sub-circuit one at a time. In our approach, two devices are applied. One is in the use of an exact min-cut graph, and the other is in the idea of keeping the number of I/O pins of the residual circuit as small as possible after one-time extraction. We implemented our algorithm in C for experiments, and tested it with several industrial cases and MCNC benchmarks. Compared to the known approach, we observed more than 10% reduction in average of the sub-circuit number.

This paper describes the circuit design procedure of the zero-current soft switching (ZCS) high frequency inverter for induction heating uses. Its output power can be regulated from its maximum to minimum by the instantaneous current vector control scheme using phase shift control between switching units at a fixed frequency. In addition, it can be safely operated since no extraordinarily high voltage or current results even at a short-circuit period at the load. Also, its overall efficiency reaches 90%. The detailed load and frequency characteristics of the inverter are elucidated by the computer-aided simulation. Then, the circuit design procedure is presented, and practical numerical examples are obtained according to this procedure which reveal that the inverter is highly practical and the design procedure is effective. The trial inverters yielding 2 kW or 4 kW were actually prepared. The observed values of the voltages and currents of the inverters were found to be in good agreement with the calculated ones. These facts certificate the validity of the proposed design procedure.

In this letter, an algorithm that estimates one of the most important channel parameters, maximum Doppler frequency, fD, is proposed. The algorithm uses phase variations of received pilot signals, which is strongly related with fD in a fading environment. In addition, a phase variation measurement method for binary phase shift keying (BPSK) modulated signals is also proposed and it makes possible to estimate fD from BPSK modulated information signals as well as unmodulated pilot signals. The results show that the proposed algorithm is very simple and shows good performance over wide Doppler frequency range.

A robust adaptive beamforming method is proposed to cancel coherent, as well as incoherent, interference using an array of arbitrary geometry. In this method, coherent interferences are suppressed by a transformation of received data with the estimates of their arrival angles and then, to reject incoherent interferences, the array output power is minimized subject to the look direction constraint in the transformed signal-plus-interference (TSI) subspace. This TSI subspace-based beamforming results in robustness to errors in the angle estimations. Its performance is theoretically examined. The theoretic results conform to simulation results. It is straightforward to apply the theoretic results to the performance analysis of subspace-based adaptive beamfomers only for incoherent interference cancellation.

This paper proposes a statistical design approach for Non-Return-to-Zero (NRZ) 40 Gbit/s systems with Forward Error Correction (FEC); the approach considers Polarization Mode Dispersion (PMD). We introduce a fluctuating PMD emulator to experimentally clarify FEC performance in PMD-limited systems. By using the proposed design approach, and considering the FEC relaxation effect on PMD, the maximum transmission distance of an NRZ 40 Gbit/s system without PMD compensation is estimated as several hundreds of km depending on the number of cable concatenations per link and the probability threshold of system acceptance.

In this letter, sampling and quantizer design for the Gaussian detection problem are considered. A constraint on the transmission rate from the remote sensor to the optimal discrete detector is assumed. The trade-off between sampling rate and the number of quantization levels is studied and illustrated by means of an example.

In this study, a hybrid genetic algorithm/neural network with fuzzy logic controller (NN-flcGA) is proposed to find the global optimum of reliability assignment/redundant allocation problems which should be simultaneously determined two different types of decision variables. Several researchers have obtained acceptable and satisfactory results using genetic algorithms for optimal reliability assignment/redundant allocation problems during the past decade. For large-size problems, however, genetic algorithms have to enumerate numerous feasible solutions due to the broad continuous search space. Recently, a hybridized GA combined with a neural network technique (NN-hGA) has been proposed to overcome this kind of difficulty. Unfortunately, it requires a high computational cost though NN-hGA leads to a robuster and steadier global optimum irrespective of the various initial conditions of the problems. The efficacy and efficiency of the NN-flcGA is demonstrated by comparing its results with those of other traditional methods in numerical experiments. The essential features of NN-flcGA namely, 1) its combination with a neural network (NN) technique to devise initial values for the GA, 2) its application of the concept of a fuzzy logic controller when tuning strategy GA parameters dynamically, and 3) its incorporation of the revised simplex search method, make it possible not only to improve the quality of solutions but also to reduce computational cost.

A 2-GHz down-converter for wide-band wireless communication systems is described. To achieve both wide-band output characteristic and LO signal suppression, an on-chip LC series resonator which is resonated at LO signal frequency and a transimpedance amplifier which is used in the output buffer circuit are used. To achieve a low sensitivity to temperature, two kinds of bias circuits; a VT reference current source and a bandgap reference current source are used. The measured 3-dB bandwidth of 600 MHz is achieved. The conversion gain varies less than 0.2 dB within 200 MHz 10 MHz and 400 MHz 10 MHz band and 0.7 dB for the temperature range from -34 to 85. At room temperature, conversion gain of 15 dB, NF of 9.5 dB and IIP3 of -5 dBm are obtained respectively. The down-converter is fabricated using Si BiCMOS process with ft=20 GHz, and it occupies approximately 1 mm2.

Much has been said and written about the changes in analog IC technology such as shrinking line widths, vanishingly low supply voltages, severe power limitations, and digital noise. But beyond these technology changes and their subsequent methodology changes, a far more subtle revolution is happening in the nature of the profession itself. Technology, software, and product evolution have all conspired to create a new kind of analog IC designer, one very different from the IC designers of the past.

A new logic-in-memory circuit is proposed for a fine-grain pipelined VLSI system. Dynamic-storage elements are distributed over a logic-circuit plane. A functional pass gate is a key component, where a linear summation and threshold function are merged compactly using charge-storage and charge-coupling effect with a DRAM-cell-based circuit structure. The use of dynamic logic based on pass-transistor network using functional pass gates makes it possible to realize any logic circuits compactly with small power dissipation. As a typical example, a 54-bit pipelined multiplier is implemented by using the proposed circuit technology. Its power dissipation and chip area are reduced to about 63 percent and 72 percent, respectively, in comparison with those of a corresponding binary CMOS implementation under 0.35-µm CMOS technology.

This paper proposes constructive timing-violation (CTV) and evaluates its potential. It can be utilized both for increasing clock frequency and for reducing energy consumption. Increasing clock frequency over that determined by the critical paths causes timing violations. On the other hand, while supply voltage reduction can result in substantial power savings, it also causes larger gate delay and thus clock must be slow down in order not to violate timing constraints of critical paths. However, if any tolerant mechanisms are provided for the timing violations, it is not necessary to keep the constraints. Rather, the violations would be constructive for high clock frequency or for energy savings. From these observations, we propose the CTV, which is supported by the tolerant mechanism based on contemporary speculative execution mechanisms. We evaluate the CTV using a cycle-by-cycle simulator and present its considerably promising potential.

We introduce PC Linux cluster computing techniques to an Evolutionary Graph Generation (EGG) system, and successfully implement the parallel version of the EGG system, called PEGG. Our survey satisfactorily shows that the parallel evolutionary approach meets our expectation that the final solutions obtained from PEGG will be as good as or better than those obtained from EGG, and that PEGG can ultimately improve the speed of evolution.

We consider to design approximation algorithms for the survivable network design problem in hypergraphs (SNDPHG) based on algorithms developed for the survivable network design problem in graphs (SNDP) or the element connectivity problem in graphs (ECP). Given an instance of the SNDPHG, by replacing each hyperedge e={v1,,vk} with a new vertex we and k edges {we, v1},, {we, vk}, we define an SNDP or ECP in the resulting graph. We show that by approximately solving the SNDP or ECP defined in this way, several approximation algorithms for the SNDPHG can be obtained. One of our results is a dmax+-approximation algorithm for the SNDPHG with dmax 3, where dmax (resp. dmax+) is the maximum degree of hyperedges (resp. hyperedges with positive cost). Another is a dmax+(rmax)-approximation algorithm for the SNDPHG, where (i)=j=1i(1/j) is the harmonic function and rmax is the maximum connectivity requirement.

There were researches that measured effort required to understand and adapt components based on the complexity of the component, which is some general criterion related to the intrinsic quality of the component to be adapted and understood. They, however, don't consider significance of the measurement attributes and user must decide reusability of similar components for himself. Therefore, in this paper, we propose a new method that can measure the DOR (Degree Of Reusability) of the components by considering the significance of the measurement attributes. We calculates the relative significance of them by using rough set and integrate the significance with the measurement value by using Sugeno's fuzzy integral. Lastly, we apply our method to the source code components and show through statistical technique that it can be used as the ordinal and ratio scale.

In this paper, we propose a method to reconstruct current distributions in the human brain from neuromagnetic measurements. The proposed method is based on the weighted lead-field synthetic (WLFS) filtering technique with the weighting factors calculated from the results of previous source space scanning. In this method, in addition to the depth normalization technique, weighting factors of the WLFS are determined by the cost values previously calculated based on the multiple signal classification (MUSIC) scan. We performed computer simulations of this method under noisy measurement conditions and compared the results to those obtained with the conventional WLFS method. The results of the simulations indicate that the proposed method is effective for the reconstruction of the current distributions in the human brain using magnetoencephalographic (MEG) measurements, even if the signal-to-noise ratio of the measured data is relatively low. We applied the proposed method to the magnetoencephalographic data obtained during a mental image processing task that included object recognition and mental rotation operations. The results suggest that the proposed method can extract the neural activity in the extrastriate visual region and the parietal region. These results are in agreement with the results of previous positron emission tomography (PET) and functional magnetic resonance imaging (fMRI) studies.

In this paper we discuss how one can delegate his power to authenticate or sign documents to others who, again, can delegate the power to someone else. A practical cryptographic solution would be to issue a certificate that consists of one's signature. The final verifier checks verifies the chain of these certificates. This paper provides an efficient and provably secure scheme that is suitable for such a delegation chain. We prove the security of our scheme against an adaptive chosen message attack in the random oracle model. Though our primary application would be agent systems where some agents work on behalf of a user, some other applications and variants will be discussed as well. One of the variants enjoys a threshold feature whereby one can delegate his power to a group so that they have less chance to abuse their power. Another application is an identity-based signature scheme that provides faster verification capability and less communication complexity compared to those provided by existing certificate-based public key infrastructure.

In this paper, we propose a channel assignment scheme for integrated voice and data traffic in reservation multiple access protocol. In the proposed scheme, a voice packet never contends with a data packet and takes over the slot which is previously assigned to a data packet. Thus, a larger number of voice terminals can be accommodated without degradation of quality and throughput even in the situation that data were integrated. We evaluate the voice packet dropping probability, throughput and packet delay through computer simulation. The results show that the proposed scheme has better performance than the conventional PRMA and DQRUMA systems.

This paper reports on clich and related mechanisms appearing in a process of human design of software. During studies on human design knowledge, the authors found frequent instance of same pattern of detailing, named clich. In our study, clich is an intermediate level of design knowledge, during a hierarchical detailing step, residing in between simple reuse and creation by micro design rules, which have already been reported. These three kinds of design knowledge are of various types and have different complexities. Discussions on them, focusing on clich type, with procedures of formation of a simple clich skeleton and generation of a clich are given. The studies show a working model of Zipf's principle, and are some trials to reveal a more detail of human designs.