In this letter we propose a filter for extracting a quasi-periodic signal from a noisy observation using wavelets. It is assumed that the instantaneous frequency of the signal is known. A particularly difficult task when the frequency and amplitude of the desired signal are varying with time is shown. The proposed algorithm is compared with three other methods.

This paper presents a system-level bus architecture validation technique and shows its application to a consumer product design. This technique enables the entire system to be validated with bus cycle accuracy using bus architecture level models derived from their corresponding behavioral level models. Experimental results from a digital still camera (DSC) system design show that our approach offers much faster simulation speed than register transfer level (RTL) simulators. Using this fast and accurate validation technique, bus architecture designs, validations and optimizations can be effectively carried out at system-level and total turn around time of system designs can be reduced dramatically.

In this paper, we propose a method to minimize multiple-valued decision diagrams (MDDs) for multiple-output functions. We consider the following: (1) a heuristic for encoding the 2-valued inputs; and (2) a heuristic for ordering the multiple-valued input variables based on sampling, where each sample is a group of outputs. We first generate a 4-valued input 2-valued multiple-output function from the given 2-valued input 2-valued functions. Then, we construct an MDD for each sample and find a good variable ordering. Finally, we generate a variable ordering from the orderings of MDDs representing the samples, and minimize the entire MDDs. Experimental results show that the proposed method is much faster, and for many benchmark functions, it produces MDDs with fewer nodes than sifting. Especially, the proposed method generates much smaller MDDs in a short time for benchmark functions when several 2-valued input variables are grouped to form multiple-valued variables.

A program is developed to simulate the signal received by a bistatic pulse radar for a defined scenario. The signal collected at the receiving antenna is calculated as a function of time by taking into account the vectorial aspect of the electromagnetic waves and various elements operating in the radar radiolink. The radar radiolink is designed in a modular structure for a general configuration where the transmitter, the target and the receiver are moving. Modules such as elements characterizing the antennas radiation or defining the target scattering can be inserted in accordance with the desired radar scenario. Then the developed model permits to simulate a wide range of radar scenarios where returns from targets and clutter can be individually processed and their characteristics can be investigated in time or frequency. The interest of this model is great because it permits, for a defined scenario, to generate radar data which can be used in signal processing algorithms for target detection, clutter suppression or target classification. This paper shows the implementation of the simulation program considering a concrete radar scenario. The presented scenario deals with the simulation of the sea clutter occurring in a bistatic radar radiolink over the sea surface. In this application where the sea surface is considered as the target, the electric field scattered from the sea surface is calculated by assuming that the surface is described by two independent scales of roughness.

In this paper, we propose a cell synthesis method for a Salicide process. Our method utilizes the local interconnect between adjacent transistors, which is available in some Salicide processes, and optimizes the transistor placement of a cell considering both area and the number of local interconnects. In this way we reduce the number of metal wires and contacts. The circuit model is not restricted to conventional series-parallel CMOS logic, and our method enables us to synthesize CMOS pass-transistor circuits. Experimental results show that our method uses the local interconnect effectively, and optimizes both cell area and metal wire length.

Aged people who live alone are in particular need of a daily health check, medication, and of warm communication with family and friends. The authors have been developing a life-support computer system with such functions. Among them, a daily health check function with the capability of measuring blood pressure, detecting diseases from coughing, and so on would in particular be very powerful for primary care. As a first step to achieving quick services for a daily health check with a personal computer, utilization of cough information is considered. Features of cough data are analyzed aiming at developing an automatic cough data detection method. This paper proposes a novel method for extracting cough signals from other types of signals. The differential coefficient of a low-pass filtered waveform is first shown to be an effective parameter for discriminating between vowel and cough signals, and the relationship between cut-off frequency and cough detection rate is clarified. This parameter is then applied to cough signals mixed with vowel signals or white noises to evaluate robustness. The evaluation tests show that the cough feature can be perfectly detected for a 20 dB S/N ratio when the cut-off frequency is set to 24 [Hz]. The experimental results suggest that the proposed cough detection method can be a useful tool as a primary care for aged people with a bronchitis like an asthmatic bronchitis and a bronchopneumonia.

Precise simulation of non-quasi-static (NQS) characteristics is crucial for the analog application of MOS transistors. This paper presents the small signal admittance model of four-terminal NQS MOS transistors by solving the differential equation derived from the primary principle. The model contains the bulk-charge effect, the mobility reduction, and the velocity saturation. The results are compared with those for the conventional quasi-static model, the BSIM3v3 NQS model, and the 2-D device simulation.

A novel residue arithmetic algorithm using radix-2 signed-digit (SD) number representation is presented. By this representation, memoryless residue arithmetic circuits using SD adders can be implemented. Conventional residue arithmetic circuits have been designed using binary number arithmetic system, but the carry propagation arises which limits the speed of arithmetic operations in residue modules. In this paper, a p-digit radix-2 SD number system is introduced to simplify the residue operation. For a modulus m, 2p-1 m 2p+2p-1-1, in a residue number system (RNS), the modulo m addition is performed by using two p-digit SD adders, one for the addition and one for the residue operation. Thus, the modulo m addition time is independent of the word length of operands. When m=2p or m= 2p 1, the modulo m addition is implemented by using only one SD adder. Moreover, a modulo m multiplier is constructed using a binary modulo m SD adder tree, and the modulo m multiplication can be performed in a time proportional to log 2 p. The VHDL implementation method for the presented algorithm is also discussed. The design and simulation results of some residue arithmetic circuits show that high speed residue arithmetic circuits can be obtained by the presented algorithms.

In this paper, we consider the coherent radar detection of rapid fluctuating signals in the Gaussian noise. This problem has been previously solved by employing the GLR technique, but we use the ALR to improve the detection performance. So, after deriving an approximate ALR detector, we compare the new detector with the GLR and Square-law detectors and we show its superiority.

To estimate moving object velocity in an image sequence is useful for a variety of applications, such as velocity measurement, computer vision and monitoring systems. An effective way is to approach it in the transform/spatiotemporal mixed domain (MixeD), which transforms the 3-D signal processing problem into 1-D complex signal processing. But it remains a problem how to select several spatial frequency points in the MixeD which may influence the accuracy of velocity estimation and object detection. In this paper, a spatial frequency selection method has been proposed, which can choose the appropriate spatial frequency points out of a number of points in MixeD automatically. So the velocity estimation problem can be addressed by solving the coupled equations established over two selected appropriate points in 2-D spatial frequency domain other than searching for the spectral energy plane over a number of points selected by experience. In this method, evaluation functions corresponding to image sequence with one moving object and two moving objects are established firstly, and the selection is then achieved by using the established evaluation functions together with a threshold. The simulation results show that the proposed method is effective on the appropriate spatial frequency selection.

This paper describes a Variable Threshold-voltage CMOS technology (VTCMOS) which controls the threshold voltage (VTH) by means of substrate bias control. Circuit techniques to combine a switch circuit for an active mode and a pump circuit for a standby mode are presented. Design considerations, such as latch-up immunity and upper limit of reverse substrate bias, are discussed. Experimental results obtained from chips fabricated in a 0.3 µm VTCMOS technology are reported. VTH controllability including temperature dependence and influence on short channel effect, power penalty caused by the control circuit, substrate current dependence at low VTH, and substrate noise influence on circuit performance are investigated. A scaling theory is also presented for use in the discussion of future possibilities and problems involved in this technology.

This paper presents a new neural network structure, called Temporal-CombNET (T-CombNET), dedicated to the time series analysis and classification. It has been developed from a large scale Neural Network structure, CombNET-II, which is designed to deal with a very large vocabulary, such as Japanese character recognition. Our specific modifications of the original CombNET-II model allow it to do temporal analysis, and to be used in large set of human movements recognition system. In T-CombNET structure one of most important parameter to be set is the space division criterion. In this paper we analyze some practical approaches and present an Interclass Distance Measurement based criterion. The T-CombNET performance is analyzed applying to in a practical problem, Japanese Kana finger spelling recognition. The obtained results show a superior recognition rate when compared to different neural network structures, such as Multi-Layer Perceptron, Learning Vector Quantization, Elman and Jordan Partially Recurrent Neural Networks, CombNET-II, k-NN, and the proposed T-CombNET structure.

In this paper, we present a low-power and area-efficient design method of embedded high-speed A/D converters for mixed analog-digital system LSI's. As the A/D converter topology, a 1.5 bit/stage interleaved pipeline A/D converter is employed, because the basic topology covers a wide range of specifications on the conversion frequency and the resolution. The design method determines the minimum DC supply current, the minimum device sizes and the minimum number of channels to meet the precision given by the specification. This paper also points out that the interleaved pipeline structure is very effective for low-power design of high-speed A/D converters whose sampling frequency is over 100 MHz.

A fully balanced (FB) transconductor using two multi-input single-ended (SE) CMOS transconductors is proposed, where the transconductors use MOS transitors operating in a triode region for achieving a wide linear input-range. SE circuits are easier to design than differential circuits and inherently reject common-mode (CM) signals. The multi-input structure is used to make a CM feedback loop and to determine an output CM voltage. A high-output-resistance current mirror is used in converting a differential signal to a single-ended signal in order to achieve a high common-mode rejection ratio (CMRR) and a high output-resistance of the transconductor. The FB transconductor achieves a 2-Vpp linear input range at a 2.5-V power supply and consumes 1.74 mA. The output resistance of the FB transconductor is 2 MΩ. It operates at 2 V with a linear input-range of 1.2 Vpp and at 1.6 V with a linear input-range of 0.9 Vpp. A 2.5-V 2.5-MHz FB Gm-C filter using the FB transconductors achieved a CMRR of 45 dB and a passband IIP3 of 32 dBm.

An 1 V, 50 MHz, 16-bit DSP core was developed using a 0.25-µm Dual Vt library, SRAM, and Mask ROM tailored for 1 V operation. The core speed was 41% enhanced using an alternate MAC and 2-stage execution pipeline. A 1.0 V to 1.5 V voltage up converter with 59% power efficiency and a 450 ps 1 V to 2.5 V level converter were implemented. An new long wire delay estimation method enhanced the synthesis. The measured power consumption at 0.9 V was 8.7 mW, which was 40% less than the power of the normal library's at 1.3 V, when the PSI-CELP CODEC firmware was run at 40 MHz.

In this paper, two distinct optical network design approaches, namely mesh and multi-ring, for survivable WDM networks are investigated. The main objective is to compare these two design approaches in terms of network costs so that their merits in practical environments can be identified. In the mesh network design, a new mathematical model based on integer liner programming (ILP) and a heuristic algorithm are presented for achieving a minimal cost network design. In the multi-ring network design, a heuristic algorithm that can be applied to large network problems is proposed. The influence of wavelength conversion and the number of wavelengths multiplexed in a fiber on system designs are also discussed. Based on the simulation results, the redundancy quantities required for full protection in multi-ring approach are significantly larger in comparison to the minimal cost mesh counterpart.

A new carrier based dynamic channel assignment for FDMA/TDMA cellular systems, called borrowing with directional carrier locking strategy, is proposed in this paper. When a call arrives at a cell and finds all voice channels busy, a carrier which consists of multiple voice channels can be borrowed from its neighboring cells for carrying the new call if such borrowing will not violate the cochannel interference constraint. Two analytical models, cell group decoupling analysis and phantom cell analysis, are constructed for evaluating the performance of the proposed strategy. Using cell group decoupling (CGD) analysis, a cell is decoupled together with its neigbors from the rest of the network for finding its call blocking probability. Unlike conventional approaches, decoupling enables the analysis to be confined to a local/small problem size and thus efficient solution can be found. For a planar cellular system with three-cell channel reuse pattern, using CGD analysis involves solving of seven-dimenional Markov chains. It becomes less efficient as the number of carriers assigned to each cell increases. To tackle this, we adopt the phantom cell analysis which can simplify the seven-dimensional Markov chain to two three-dimentional Markov chains. Using phantom cell analysis for finding the call blocking probability of a cell, two phantom cells are used to represent its six neighbors. Based on extensive numerical results, we show that the proposed strategy is very efficient in sharing resources among base stations. For low to medium traffic loads and small number of voice channels per carrier, we show that both analytical models provide accurate prediction on the system call blocking probability.

This paper investigates noise enhancement factors of a zero-forcing detector and a decision feedback detector for synchronous Multiple Input Multiple Output (MIMO) channels. It is first shown that the zero-forcing and decision feedback detectors can be implemented in a vector digital filter form, and the noise enhancement factors with the detectors can easily be calculated by using the vector digital filter form. This paper then applies the zero-forcing and decision feedback detectors to the signal detection of a frequency-overlapped multicarrier signaling (FOMS) system. The normalized noise enhancement factor, which is given as a product of the noise enhancement and bandwidth reduction factors, is shown to be smaller with the decision feedback detector than the zero-forcing detector. Results of computer simulations conducted to evaluate bit error rate (BER) performances with the two detectors are also shown together with the BER performance with a conventional channel-by-channel detector.

The problem of self-timed implementation of Boolean functions is explained. The notions of combinational delay-insensitive code and delay-insensitive function are defined, giving precise conditions under which memoryless self-timed implementation of Boolean functions is feasible. Examples of combinational delay-insensitive code and delay-insensitive function are given. Generic design style, using standard CAD library, for constructing quasi delay-insensitive self-timed function blocks is suggested. Our design style is compared to other self-timed function block design styles.

In this paper, we discuss on the realization of reduced peak power transmission for the multicarrier systems. Since the signals have large amplitude fluctuations in conventional multicarrier systems, signals amplified by a nonlinear amplifier are greatly distorted, resulting in severe performance degradation. In order to avoid this large amplitude fluctuation, we propose a scheme for reducing the nonlinear distortion by using the set of the signal point series which show low peak to mean envelope power ratio (PMEPR) value. In this system, one symbol is transmitted with multicarriers and the received signal is detected with maximum likelihood sequence detection.