The glottal closure instants (GCIs) obtained from the wavelet analysis of speech signal are investigated in comparison with those obtained from the EGG signal. Experimental results have shown that about 96% of GCIs with wavelet transformed speech signal is located within 0.5 ms with respect to the GCIs with EGG signal.

This paper presents an algorithm for the scan-chain optimization problem in multiple-scan design methodology. The proposed algorithm, which consists of four phases, first determines pairs of scan-in and scan-out pins (Phase 1), and then assigns flip-flops to scan-paths by using a graph theoretical method (Phase 2). Next the algorithm decides connection-order of flip-flops in each scan-path by using TSP (Traveling Salesman Problem) heuristics (Phase 3), and finally exchanges flip-flops among scan-paths in order to reduce total scan-path length (Phase 4). Experiments using actual design data show that, for ten scan-paths, our algorithm achieved a 90% reduction in scan-test time at the expense of a 7% total scan-path length increase as compared with the length of a single optimized scan-path. Also, our algorithm produced less total scan-path length than other three possible algorithms in a reasonable computing time.

The subliminal channel is one of the methods for hiding a message in other messages. Simmons has shown conjectures on the upper bound to the bandwidth of a subliminal channel. This paper proposes a new broad-band subliminal channel embedded in the ESIGN. The bandwidth of the proposed subliminal channel is wider than that of the previous one, and it exceeds the upper bound that Simmons has conjectured. Namely, we disprove the conjectures due to Simmons. We also show that it is possible to construct the subliminal channel even if the transmitter and the subliminal receiver do not have any key in common.

This paper presents unified VLSI architectures which can efficiently realize some widespread one-dimensional (1-D) and two-dimensional (2-D) real discrete trigonometric transforms, including the discrete Hartley transform (DHT), discrete sine transform (DST), and discrete cosine transform (DCT). First, succinct and unrestrictive Clenshaw's recurrence formula along with the inherent symmetry of the trigonometric functions are adequately employed to render efficient recurrences for computing these 1-D RDTT. By utilizing an appropriate row-column decomposition approach, the same set of recurrences can also be used to compute both of the row transform and column transform of the 2-D RDTT. Array architectures, basing on the developed recurrences, are then introduced to implement these 1-D and 2-D RDTT. Both architectures provide substantial hardware savings as compared with previous works. In addition, they are not only applicable to the 1-D and 2-D RDTT of arbitrary size, but they can also be easily adapted to compute all aforementioned RDTT with only minor modifications. A complete set of input/output (I/O) buffers along with a bidirectional circular shift matrix are addressed as well to enable the architectures to operate in a fully-pipelined manner and to rectify the transformed results in a natural order. Moreover, the resulting architectures are both highly regular, modular, and locally-connected, thus being amenable to VLSI implementations.

In pattern recognition using neural networks, it is very difficult for researchers or users to design optimal neural network architecture for a specific task. It is possible for any kinds of neural network architectures to obtain a certain measure of recognition ratio. It is, however, difficult to get an optimal neural network architecture for a specific task analytically in the recognition ratio and effectiveness of training. In this paper, an evolutional method of training and designing feedforward neural networks is proposed. In the proposed method, a neural network is defined as one individual and neural networks whose architectures are same as one species. These networks are evaluated by normalized M. S. E. (Mean Square Error) which presents a performance of a network for training patterns. Then, their architectures evolve according to an evolution rule proposed here. Architectures of neural networks, in other words, species, are evaluated by another measurement of criteria compared with the criteria of individuals. The criteria assess the most superior individual in the species and the speed of evolution of the species. The species are increased or decreased in population size according to the criteria. The evolution rule generates a little bit different architectures of neural network from superior species. The proposed method, therefore, can generate variety of architectures of neural networks. The designing and training neural networks which performs simple 3 3 and 4 4 pixels which include vertical, horizontal and oblique lines classifications and Handwritten KATAKANA recognitions are presented. The efficiency of proposed method is also discussed.

In this paper, we study the link capacity assignment problem in packet-switched networks (CA problem) focusing on the case where link cost function is a piecewise linear concave function. This type of cost function arises in many communication network design problems such as those arising from developments in communication transmission technologies. It is already known that the method of link set assignment is applicable for solving the CA problem with piecewise linear convex cost function. That is, each link in the network is assigned to one of a group of specific sets, and checked for link set contradiction. By extending the method of link set assignment to the case of piecewise linear concave cost function, an important characteristic of the optimal solution of the CA problem is derived. Based on this characteristic, the non-differentiable link cost function can be treated as a differentiable function, and a heuristic algorithm derived from the Lagrange multiplier method is then proposed. Although it is difficult to determine the global optimum of the CA problem due to its non-convexity, it is shown by numerical results that the solution obtained from the proposed algorithm is very close to the global optimum. Moreover, the computation time is linearly dependent on the number of links in the problem. These performances show that the proposed algorithm is very efficient in solving the CA problem, even in the case of large-scale networks.

This paper describes the benefit of utilizing the unary function generators in a multiple-valued Programmable Logic Array (PLA). We will clarify the most suitable PLA structure in terms of the array size. The multiple-valued PLA considered here has a structure with two types of function generators (literal and unary function generators), a first-level array and a second-level array. On investigating the effectiveness to reduce the array size, we can pick up four form PLAs: MAX-of-TPRODUCT form, MIN-of-TSUM form, TSUM-of-TPRODUCT form and TPRODUCT-of-TSUM form PLAs among possible eight form PLAs constructing from the MAX, MIN, TSUM and TPRODUCT operators. The upper bound of the array sizes with v UGs is derived as (log2ppv + p(n-v) + 1) pn-1 to realize any n-variable p-valued function. Next, experiments to derive the smallest array sizes are done for 10000 randomly generated functions and 21 arithmetic functions. These results conclude that MAX-of-TPRODUCT form PLA is the most useful in reducing the array size among the four form PLAs.

This paper presents a new number representation called the Signed-Weight (SW) number system, which is useful for designing configurable counter-tree architectures for digital signal processing applications. The SW number system allows the unified manipulation of positive and negative numbers in arithmetic circuits by adjusting the signs assigned to individual digit positions. This makes possible the construction of highly regular arithmetic circuits without introducing irregular arithmetic operations, such as negation and sign extension in the two's complement representation. This paper also presents the design of a Field-Programmable Digital Filter (FPDF) architecture--a special-purpose FPGA architecture for high-speed FIR filtering--using the proposed SW arithmetic system.

This paper presents a low-power video A/D conversion technique using features of moving pictures. Neighboring frames in typical video sequences and neighboring pixels in each video frame are highly correlated. This property is effectively used for the video A/D conversion to reduce the number of comparators and the resulting power consumption. A set of reference voltages is given to a comparator array so that the iterative A/D conversion converges in the logarithmic order of the prediction error. Simulation results using standard moving pictures showed that the average number of iterations for the A/D conversion is less than 3 for all the moving pictures tested. In the proposed 12 b A/D converter, the number of comparators can be reduced to about 1/5 compared with that of the two-step flash A/D converters, which are commonly used for video applications. The A/D converter is particularly useful for the integration to CMOS image sensors.

This letter proposes an integrated approach to multimedia ATM network design. An optimization model that combines the physical layer design with the logical layer design is developed. A key feature of the model is that the objective to be maximized is a profit function. It includes more comprehensive cost functions for the physical and logical layers. A simple heuristic algorithm to solve the model is presented. It should be useful in practice for network designers and operators. Some numerical examples are given to illustrate the application of the model and the algorithm.

This paper treats the systematic design of chaos generators which are capable of generating continuous-time signals with prescribed probability density function and power density spectra. For a specific signal model a statistical analysis is performed such that the inverse problem, i. e. the calculation of the model parameters from prescribed signal characteristics, can be solved. Finally from the obtained model parameters and the model structure the signal generating system is constructed. The approach is illustrated by several examples.

A compact residue arithmetic multiplier based on the radix-4 signed-digit arithmetic is presented. Conventional residue arithmetic circuits have been designed using binary number arithmetic system, but the carry propagation arises which limits the speed of arithmetic operations in residue modules. In this paper, two radix-4 signed-digit (SD) number representations, {-2,-1,0,1,2} and {-3,-2,-1,0,1,2,3}, are introduced. The former is used for the input and output, and the later for the inner arithmetic circuit of the presented multiplier. Integers 4p and 4p 1 are used as moduli of residue number system (RNS), where p is a positive integer and both circuits for partial product generation and sum of the partial products can be efficiently constructed by using the multiple-valued current-mode circuits. The modulo m addition, m=4p or m=4p 1, can be performed by an SD adder or an end-around-carry SD adder with the multiple-valued circuits and the addition time is independent of the word length of operands. The modulo m multiplier can be compactly constructed using a binary tree of the multiple-valued modulo m SD adders, and consequently the modulo m multiplication is performed in O(log p) time. The number of MOS transistors required in the presented residue arithmetic multiplier is about 86p2 + 66p.

This paper presents a novel method of an on-sensor motion vector estimation. One of the key techniques is an iterative block matching algorithm using high-speed interpolated pictures. This technique allows us to estimate the video-rate (30 frame/s) motion vectors accurately from the motion vectors obtained at high-speed frames. The proposed iterative block matching reduces the computational complexity by a factor of more than one tenth compared to the conventional full search block matching algorithm. This property is particularly useful for the reduction of the power dissipation of video encoder. Another proposed technique is a high-speed non-destructive image sensing. This technique is essential to obtain high-speed interpolated pictures while maintaining high image quality in video-rate image sensing. The estimated power dissipation of the designed CMOS image sensor is sufficiently low, allowing us to achieve a totally low-power design of one-chip CMOS cameras integrating an image sensor and a video encoder.

In this paper, we present the theoretical development to stabilize a class of uncertain time-delay system. The system under consideration is described in state space model containing distributed delay, uncertain parameters and disturbance. The main idea is to transform the system state into an equivalent one, which is easier to analyze its behavior and stability. Then, a computational method of robust controller design is presented in two parts. The first part is based on solving a Riccati equation arising in the optimal control theory. In the second part, the finite dimensional Lyapunov min-max approach is employed to cope with the uncertainties. Finally, we show how the resulting control law ensures asymptotic stability of the overall system.

This paper explores a possibility of constructing massively parallel molecular computing systems using molecular electronic devices called enzyme transistors. The enzyme transistor is, in a sense, an artificial catalyst which selects a specific substrate molecule and transforms it into a specific product. Using this primitive function, various active continuous media for signal transfer/processing can be realized. Prominent examples discussed in this paper are: (i) Turing pattern formation and (ii) excitable wave propagation in a two-dimensional enzyme transistor array. This paper demonstrates the potential of enzyme transistors for creating reaction-diffusion dynamics that performs useful computations in a massively parallel fashion.

Fractal immittance, expressed by an admittance sa (0<|a|<1), is simulated by the analog circuits composed of finite numbers of conventional elements, resistance R, capacitance C and inductance L, based on the distributed-relaxation-time models. The correlation between the number of R-C or R-L pairs and the optimum pole interval to give the widest bandwidth is estimated for each a-value by the numerical calculation for each circuit against a given criterion with respect to the phase angle. It is found that the bandwidth of 5 decades with a phase-angle error of 1 can be composed for |a|=0.1-0.9 using eighteen pairs or less of the elements.

In the literature [9], the optimum discrete interpolation of one-dimensional signals is presented which minimizes various measures of approximation error simultaneously. In the discussion, the ratio λ of the weighted norm of the approximation error and that of the corresponding input signal plays an essential role to determine the structure of the set of signals. However, only the upper bound of λ is provided in [9]. In this paper, we will present more exact and systematic discussion of the optimum discrete interpolation of one-dimensional signals which minimizes various measures of approximation error at the same time. In this discussion, we will prove that the exact value of λ is identical with the upper limit, for ω (|ω| π), of the largest eigen value of a matrix including the weighting function W(ω) and the Fourier transforms of the optimum interpolation functions. Further, we will give a sufficient condition for W(ω) under which the ratio λ is equal to one, where the approximation error, if it is interpolated by sinc, is included in the set of band-limited signals defined by W(ω). Finally, as application of the presented approximation, we will propose a direction to interactive signal processing on Internet and a transmultiplexer system included in it. The transmultiplexer system included in this discussion can realize flexible arrangement of sub-bands which is inevitable in realizing the above proposal on interactive signal processing.

In this paper, a new gradient-based adaptive algorithm for the estimation of discrete Fourier coefficients (DFC) of a noisy sinusoidal signal is proposed based on a summed least mean squared error criterion. This algorithm requires exactly the same number of multiplications as the conventional LMS algorithm, and presents much improved performance in both white and colored noise environments at the expense of some additional memories and additions only. We first analyze the performance of the conventional LMS algorithm in colored additive noise, and point out when its performance deteriorates. Then, a summed least mean squared error criterion is proposed, which leads to the above-mentioned new gradient-based adaptive algorithm. The performance of the proposed algorithm is also analyzed for a single frequency case. Simulation results are provided to support the analytical findings and the superiority of the new algorithm.

Wavelet filters used in usual applications are not time-varying filters. In this paper, we present a novel method to design biorthogonal wavelet filters which are orthogonal to the input signals. We call newly designed filters time-varying lifting wavelet filters (TVLWF). Their feature is to vary the wavelet filters adapting to the input signal by tuning free parameters contained in the lifting scheme developed by Sweldens. These filters are almost compact support and perfect reconstruction. By using TVLWF, we demonstrate an application to data compression of electrocardiogram (ECG) which is one of the semi-periodic time-series signals and show that the time-varying system can be constructed easily and the proposed method is very useful for data compression.

This paper reports on time-space conversion-based differential processing of optical signals using a high-resolution arrayed-waveguide grating (AWG) and a spatial filter at a wavelength of 1.55 µm. We clarify the advantages of the AWG device and show where it is applicable. In order to reduce loss at the spatial filter, we propose a new phase-only filter that functions as a differential filter. The difference between the exact differential filter and the proposed phase-only filter is calculated theoretically. We confirm experimentally that the optical pulse can be differentiated by the proposed filter. For application of differential processing, we also proposed a phase modulation to amplitude modulation (PM-AM) conversion and demonstrated the PM-AM conversion at 10 Gbit/s signals using a PSK-non-return-to-zero (NRZ) format.