The relationship between the change in transistor operation regions and the fault behavior of a mixed-signal circuit having a bridging fault was investigated. We also discussed determination of transistors to be observed for estimating the fault behavior. These results will be useful for modeling faulty behaviors and analyzing and diagnosing faults in mixed-signal circuits.

Formal description techniques (FDTs) such as VDM, Z, LOTOS, etc are powerful to develop safety-critical systems since they have strict semantics and mathematical reasoning basis. However, they have no methods or guides how to construct specifications unlike specification and design methods such as Object-Oriented Modeling and Technique (OMT), and that makes it difficult for practitioners to compose formal specifications. One of the solutions is to connect formal description techniques with some existing methods. This paper discusses a technique how to integrate FDTs with specification and design methods such as OMT so that we can have new methods to support writing formal specifications. The integration mechanism is based on transformation rules of specification documents produced following methods into the descriptions written in formal description techniques. The transformation rules specify the correspondences on two meta models; of methods and of formal description techniques, and are described as graph rewriting rules. As an example, we pick up OMT as a method and LOTOS as a FDT and define the transformation rule on their meta models.

In this paper, we propose a new secure server-aided RSA secret computation protocol which guards against not only the attacks in [1],[2],[15],[18] but also the new powerful active attacks in [3],[4]. The new protocol is also efficient to support high security level.

Signal conservation logic (SCL) is a model of logic for the physical world subject to the matter conservation law. This letter proves that replication, complementary replication, and computational universality called elemental universality are equivalent in SCL. Since intelligence has a close relation to computational universality, the presented theorem may mean that life under the matter conservation law eventually acquires some kind of intelligence.

In digital signal processing, bit width of intermediate variables should be longer than that of input and output variables in order to execute intermediate operations with high precision. Then a processor core for digital signal processing is required to have two types of register files, one of which is used by input and output variables and the other one is used by intermediate variables. This paper proposes a hardware/software cosynthesis system for digital signal processor cores with two types of register files. Given an application program and its data, the system synthesizes a hardware description of a processor core, an object code running on the processor core, and software environments. A synthesized processor core can be composed of a processor kernel, multiple data memory buses, hardware loop units, addressing units, and multiple functional units. Furthermore it can have two types of register files RF1 and RF2. The bit width and number of registers in RF1 or RF2 will be determined based on a given application program. Thus a synthesized processor core will have small area with keeping high precision of intermediate operations compared with a processor core with only one register file. The experimental results demonstrate the effectiveness of the proposed system.

A nonlinear multiple complex sinusoidal estimator (NMSE) is proposed, as an extended and improved version with system noise of the single sinusoidal estimator previously presented by the author, for extracting multiple complex sinusoids in white noise. This estimator is derived by applying an extended complex Kalman filter (ECKF) to a noisy multiple complex sinusoidal model with state-representation, where the model becomes a nonlinear stochastic system. Proof of the stability is given by using a structure of the state-space signal model and Lyapunov techniques. Also, computer simulations demonstrate the effectiveness of the NMSE from various points of view.

This paper presents an architecture for a single-chip MPEG-2 video encoder and demonstrates its flexibility and usefulness. The architecture based on three-layer cooperation provides flexible data-transfer that improves the encoder from the standpoints of versatility, scalability, and video quality. The LSI was successfully fabricated in the 0.25-µm four-metal CMOS process. Its small size and its low power consumption make it ideal for a wide range of applications, such as DVD recorders, PC-card encoders and HDTV encoders.

Low Power design has emerged as a both practically and theoretically attractive theme in modern LSI system design. This paper presents system level power optimization techniques. A brief survey of system level low power design approaches and several examples in detail are described. It reviews some techniques that have been proposed to overcome the power issue and gives guideline for prospective system level solutions.

A tail current source is often employed for many analog building blocks. It can limit the increase of excess power. It can also improve CMRR and PSRR. In this paper, we propose a very high output impedance tail current source for low voltage applications. The proposed tail current source has almost the same output impedance as the conventional cascode type tail current source in theory. Simulation results show that the output impedance of the proposed circuit becomes 1.28 GW at low frequencies. Applying the proposed circuit to a differential amplifier, the CMRR is enhanced by 66.7 dB, compared to the conventional differential amplifier. Moreover, the proposed circuit has the other excellent merit. The output stage of the proposed tail current source can operate at VDS(sat) and a quarter of VDS(sat) of the simple current source in theory and simulation, respectively. For example, in the simulation, when the reference current IREF is set to 100µA, the minimum voltage of the simple current source approximates 0.4 V, whereas that of the proposed current source approximates 0.1 V. Thus, the dynamic range can be enlarged by 0.3 V in this case. The value is still enough large value for low voltage applications. Hence, the proposed tail current source is suitable for low voltage applications.

In order to investigate the possibility of avatar communication using sign-language, in this paper, we develop a sign-language chatting system on the Internet using CG aniamtion techniques between Korea and Japan. We construct the system in server-client architecture, where images of Korean or Japanese sign-language are analyzed into a series of parameters for sign-language animation by server. We transmit the parameters, which are text data instead of images or their compression, to clients and regenerate the corresponding CG animation using the received data. The chatting system is implemented with Visual C++ 5.0 on Windows platforms. Experimental results show that the sign-language could be used as a communication means between avatars of different languages.

An increase in high quality of service (QoS) applications such as video conferencing and distribution, and the evolution of the Internet have popularized ATM-LAN use based on the private network node interface (PNNI). Also in public networks, which serve as backbone networks for LANs, ATM technology is being introduced for high-speed and broadband communication. These situations lead to a great demand for economically and seamlessly interconnecting remote ATM-LANs via ATM public networks, which are based on broadband ISDN user part (BISUP). This paper discusses a method of peer group configuration method for such internetworking architecture that can avoid an overload of the PNNI routing processing in each peer group. The paper also proposes a method for seamless interconnection of remote ATM-LANs. In this method, complete PNNI signaling and routing is executed between a local switch (LS) in a public network and each ATM-LAN. It also can reduce the PNNI routing processing load on each public network by emulating PNNI routing and signaling between LSs.

This paper summarizes power reduction methods applicable for VLSI bus systems in terms of reduction of signal swing, effective capacitance reduction and reduction of signal transition, which have been studied in authors' research group. In each method the basic concept is reviewed quickly along with some examples of its application. A future perspective is also described in conclusion.

A lower impedance terminal is necessary for an input terminal of current-mode circuits and an output terminal of voltage-mode circuits to reduce an error and distortion in analog signal processing. Thus, the CMOS circuit with a very low impedance terminal (VLIT circuit) is a useful analog building block to achieve the above purpose. The very low impedance terminal in the VLIT circuit is performed by a shunt-series feedback configuration. However, the feedback generates a problem of instability and/or oscillation at the same time. The problem can be removed by a phase compensation capacitor as known well, but the capacitor is not desirable for integrated circuits due to its large area. This paper proposes a new phase compensation technique for the VLIT circuit. The proposed technique does not need any capacitors to obtain a sufficient phase margin, and instead gives us the appropriate transistor sizes (Width and length of the gate). As a result, the VLIT circuit has an enough phase margin and operates stably.

The purpose of this paper is to deal with the problem of recovering a signal from its noisy version. One example is to restore old images degraded by noise. The recovery solution is given within the framework of series expansion and we shall show that for the general case the recovery functions have to be elements of an extended pseudo biorthogonal basis (EPBOB) in order to suppress efficiently the corruption noise. After we discuss the different situations of noise, we provide some methods to construct the optimal EPBOB in order to deal with these situations.

This paper describes the design principles, the specification, and evaluations of a new 128-bit block cipher E2, which was proposed to the AES (Advanced Encryption Standard) candidates. This algorithm supports 128-bit, 192-bit, and 256-bit secret keys. The design philosophy of E2 is highly conservative; the structure uses 12-round Feistel as its main function whose round function is constructed with 2-round SPN structure, and initial/final transformational functions. E2 has practical security against differential attack, linear attack, cryptanalysis with impossible differential, truncated differential attack, and so on. Furthermore, E2 can be implemented efficiently and flexibly on various platforms because the primitive operations involve byte length processing.

The paper shows some of benefits of multi-unitary decomposition in signal analysis applications. It is emphasized that decompositions of complex discrete-time signals onto a single basis provide an incomplete and in such way potentially misleading image of the signals in signal analysis applications. It is shown that the multi-unitary decimated filter banks which decompose the analyzed signal onto several bases of the given vector space can serve as a tool which provides a more complete information about the signal and at the same time the filter banks can enjoy efficient polyphase component implementation of maximally decimated, i. e. nonredundant, filter banks. An insight into the multi-unitary signal decomposition is provided. It is shown that the multiple-bases representation leads to an efficient computation of frequency domain representations of signals on a dense not necessarily uniform frequency grid. It is also shown that the multiple-bases representation can be useful in the detection of tones in digital implementations of multifrequency signaling, and in receivers of chirp systems. A proof is provided that there are possible benefits of the multiple-bases representations in de-noising applications.

High-speed low-power matched filter plays an important role in the fast despreading of spread-signals in wideband code division multiple access (W-CDMA) mobile communications. In this paper, we describe the algorithm and the VLSI-architecture of a complex matched filter chip implemented by our proposed digital-controlled analog parallel operational circuits. The complex matched filter VLSI with variable taps from 4 to 128 is developed for despreading QPSK-modulated spread-signals for W-CDMA communications, which is fabricated by a 2-metal 0.8 µm CMOS technology. The dissipation power of the chip is 225 mW and 130 mW when it operates at the chip-rate of 20 MHz with the supply voltages of 3.0 V and 2.5 V, respectively, and it can be furthermore reduced to 62 mW at chip rate of 10 MHz when the supply voltage is lowered to 2.2 V. The 3-dB cut-off frequency of the fabricated chip is higher than 20 MHz for both 3.0 V and 2.5 V supplies. Comparing to pure digital matched filters, the massive and high-speed despreading operations of the spread-signals are directly carried out in analog domain. As a result, two high-speed analog-to-digital (A/D) converters operating at chip rate are omitted, the inner signal paths and the total dissipation power are greatly reduced.

This paper reviews design aspects of computational discovery systems through the analysis of some successful discovery systems. We first review the concept of viewscope/view on data which provides an interpretation of raw data in a specific domain. Then we relate this concept to the KDD process described by Fayyad et al. (1996) and the developer's role in computational discovery due to Langley (1998). We emphasize that integration of human experts and discovery systems is a crucial problem in designing discovery systems and claim together with the analysis of discovery systems that the concept of viewscope/view gives a way for approaching this problem.

This paper reports the design and characteristics of an aerial optical drop cable incorporating electric power wires, which was developed for a new π-system. The new system is called the power supply HUB π-system, in which commercial AC electric power is received at a central location of several optical network units (ONUs), and is distributed to each ONU by the aerial optical/electric drop cable. We describe the requirements for the cable, which guarantee a 20-year lifetime. We designed the cross-sectional structure of the cable, based on system requirements and operation requirements, and determined the strength wire type and diameter, based on the optical fiber failure prediction theory and a cable strain requirement. We confirmed that the cables, manufactured as a trial, have stable characteristics, which satisfy the above requirements. The optical/electric drop cables will be introduced in autumn 1999.

We propose an untraceable electronic money system. Our system uses the partially blind signature based on the discrete logarithm problem, and applies secret key certificates to the payment protocol.