Physical defects that are not covered by stuck-at fault or bridging fault model are increasing in LSI circuits designed and manufactured in modern Deep Sub-Micron (DSM) technologies. Therefore, it is necessary to target non-stuck-at and non-bridging faults. A stuck-open is one such fault model that captures transistor level defects. This paper presents two methods for maximizing stuck-open fault coverage using stuck-at test vectors. In this paper we assume that a test set to detect stuck-at faults is given and we consider two formulations for maximizing stuck-open coverage using the given test set as follows. The first problem is to form a test sequence by using each test vector multiple times, if needed, as long as the stuck-open coverage is increased. In this case the target is to make the resultant test sequence as short as possible under the constraint that the maximum stuck-open coverage is achieved using the given test set. The second problem is to form a test sequence by using each test vector exactly once only. Thus in this case the length of the test sequence is maintained as the number of given test vectors. In both formulations the stuck-at fault coverage does not change. The effectiveness of the proposed methods is established by experimental results for benchmark circuits.

This paper proposes an efficient design algorithm for power/ground (P/G) network synthesis with dynamic signal consideration, which is mainly caused by Ldi/dt noise and Cdv/dt decoupling capacitance (DECAP) current in the distribution network. To deal with the nonlinear global optimization under synthesis constraints directly, the genetic algorithm (GA) is introduced. The proposed GA-based synthesis method can avoid the linear transformation loss and the restraint condition complexity in current SLP, SQP, ICG, and random-walk methods. In the proposed Hybrid Grid Synthesis algorithm, the dynamic signal is simulated in the gene disturbance process, and Trapezoidal Modified Euler (TME) method is introduced to realize the precise dynamic time step process. We also use a hybrid-SLP method to reduce the genetic execute time and increase the network synthesis efficiency. Experimental results on given power distribution network show the reduction on layout area and execution time compared with current P/G network synthesis methods.

Functional and formal verification are important methodologies for complex mixed-signal design validation. However the industry is still verifying such systems by pure simulation. This process lacks on error localization and formal verifications methods. This is the existing verification gap between the analog and digital blocks within a mixed-signal system. Our approach improves the verification process by creating temporal properties named mixed-signal assertions which are described by a combination of digital assertions and analog properties. The proposed method is a new assertion-based verification flow for designing mixed-signal circuits. The effectiveness of the approach is demonstrated on a Σ/Δ-converter.

This article presents an indoor positioning and communication platform, using fluorescent lights. We set up a practical implementation of a VLC (Visible Light Communication) system in a University building. To finalize this work, it is important that we analyze the properties of the reception signal, especially the length of the data string that can be received at different walking speed. In this paper, we present a model and a series of formulae for analyzing the relationship between positioning signal availability and other important parameters, such as sensor angle, walking speed, data transmission rate, etc. We report a series of real-life experiments using VLC system and compare the results with those generated by the formula. The outcome is an improved design for determination of the reception area with more than 97% accurate signals, and an optimal transmission data length, and transmission rate.

A formal approach for specifying and reasoning about earth-friendly logistics management systems is presented. To reduce fossil fuel consumption and carbon dioxide emissions resulting from transport, we must enhance the transport efficiency of trucks, which play an essential role as carriers in modern logistics services. This paper addresses the milk-run approach. It is one of the most effective and popular solutions to this problem, but it makes it be complicated to implement in a logistics management system. We propose a language for specifying the routes of trucks and an order relation between the requirements of routes and the possible routes of trucks. The former is formulated as process calculus and the latter selects suitable trucks according to their routes.

This paper simulates the dynamic behavior of the operating mechanism of ACB, and analyzes factors influencing the mechanism's operating time. First, it builds a dynamic model for the mechanism with virtual prototype technology. Experiment validation is carried out to prove the correctness of the model. Based on this model, it puts emphasis on analyzing the influence of electro-dynamic repulsion force on the operating time of the mechanism. Simulation and experimental results show that after adding electric repulsion force to the model, the operating time is shortened about 1.1 ms. Besides the repulsion force, other influencing factors including the stiffness of opening spring, locations of every key axis, mass and centroidal coordinates of every mechanical part are analyzed as well. Finally, it makes an optimum design for the mechanism. After optimization, the velocity of operating mechanism is improved about 6.7%.

We have developed a compact double-gate metal-oxide-semiconductor field-effect transistor model for circuit simulation considering the volume inversion effect by solving the Poisson equation explicitly. It is verified that applied voltage dependence of the calculated potential values both at the surface and at the center of the silicon layer reproduce 2 dimensional device simulation results for any device structure, confirming the validity of the model for device optimization.

The redox (Reduction-Oxidation) flow battery is one of the most promising rechargeable batteries due to its ability to average loads and output of power sources. The transient characteristics are well known as the remarkable feature of the battery. Then it can also compensate for a sudden voltage drop. The dynamics are governed by the chemical reactions, fluid flow, and electrical circuit of its structure. This causes the difficulty of the analysis at transient state. This paper discusses the transient behavior of the redox flow battery based on chemical reactions. The concentration change of vanadium ions depends on the chemical reactions and the flow of electrolysis solution. The chemical reaction rate is restricted by the attached external electric circuit. In this paper, a model of the transient behavior is introduced. The validity of the derived model is examined based on experiments for a tested micro-redox flow battery system.

AlN/GaN Metal Insulator Semiconductor Field Effect Transistors (MISFETs) were designed, simulated and fabricated. DC, S-parameter and power measurements were also performed. Drift-diffusion simulations using DESSIS compared AlN/GaN MISFETs and Al32Ga68N/GaN Heterostructure FETs (HFETs) with the same geometries. The simulation results show the advantages of AlN/GaN MISFETs in terms of higher saturation current, lower gate leakage and higher transconductance than AlGaN/GaN HFETs. First results from fabricated AlN/GaN devices with 1 µm gate length and 200 µm gate width showed a maximum drain current density of 380 mA/mm and a peak extrinsic transconductance of 85 mS/mm. S-parameter measurements showed that current-gain cutoff frequency (fT) and maximum oscillation frequency (fmax) were 5.85 GHz and 10.57 GHz, respectively. Power characteristics were measured at 2 GHz and showed output power density of 850 mW/mm with 23.8% PAE at VDS = 15 V. To the authors knowledge this is the first report of a systematic study of AlN/GaN MISFETs addressing their physical modeling and experimental high-frequency characteristics including the power performance.

Transmission performance of amplitude and phase shift keying (APSK) format is studied theoretically. The extinction ratio of the amplitude shift keying (ASK) signal of the APSK format causes a trade-off of the performance between the ASK and the phase shift keying (PSK) signal of the APSK format. Then, zero-nulling method is proposed to improve the performance of the APSK format, and its effectiveness is confirmed by the numerical simulation.

UHF radio frequency identification (RFID) has gathered significant interest in the field of long-distance automatic identification applications. Since UHF RFID shares the frequency band with other RFID and/or other wireless systems, it is important to determine how much interference can be applied without causing a significant degradation of anti-collision speed. In this paper, the permissible link quality for RFID anti-collision in a practical environment is discussed by considering an erroneous communication link, taking into account of bit encoding and the type of interference. We approach the quantification of permissible link quality experimentally along with protocol simulations and the mathematical analyses. An international standard protocol, employing frame slotted ALOHA, was used as the air protocol. For these investigations, the present authors developed a protocol simulator. The simulation results were compared with analytical values based on Poisson distribution. The investigation in the return (tag to reader) link, and the forward (reader to tag) link, were analyzed separately. As result of the protocol simulation, it is generally important to secure the Pulse Error Rate 10-4 or better in both return and forward links for the anti-collision of 64 or less tags. The quality of the return link may be relaxed when the application does not require fast anti-collision. The degradation of the forward link, on the other hand, may entail loss of important commands, resulting in extremely slow anti-collision. It is measured experimentally that the required link quality can be relaxed by up to 10 dB in the return links and by 5 dB in the forward link when the primary source of interference originates in the interfering readers.

This paper investigates the design curves of the class DE amplifier with the nonlinear shunt capacitances for any output Q and any grading coefficient m of the diode junction in the MOSFET. The design curves are derived by the numerical calculation using Spice. The results of this paper have two important meanings. Firstly, it is clarified that the nonlinearities of the shunt capacitances affect the design curves of the class DE amplifier, especially, for low output Q. Moreover, the supply voltage is a quite important parameter to design the class DE amplifier with the nonlinear shunt capacitances. Secondly, it is also clarified that the numerical design tool using Spice, which is proposed by authors, can be applied to the derivation of the design curves. This shows the possibility of the algorithm to be a powerful tool for the analysis of the class E switching circuits. The waveforms from Spice simulations denote the validity of the design curves.

In general, we do not know which fault model can explain the cause of the faulty values at the primary outputs in a circuit under test before starting diagnosis. Moreover, under Built-In Self Test (BIST) environment, it is difficult to know which primary output has a faulty value on the application of a failing test pattern. In this paper, we propose an effective diagnosis method on multiple fault models, based on only pass/fail information on the applied test patterns. The proposed method deduces both the fault model and the fault location based on the number of detections for the single stuck-at fault at each line, by performing single stuck-at fault simulation with both passing and failing test patterns. To improve the ability of fault diagnosis, our method uses the logic values of lines and the condition whether the stuck-at faults at the lines are detected or not by passing and failing test patterns. Experimental results show that our method can accurately identify the fault models (stuck-at fault model, AND/OR bridging fault model, dominance bridging fault model, or open fault model) for 90% faulty circuits and that the faulty sites are located within two candidate faults.

In this paper, the development, long-term operation and portability of a practical ASR application in a real environment is investigated. The target application is a speech-oriented guidance system installed at the local community center. The system has been exposed to ordinary people since November 2002. More than 300 hours or more than 700,000 inputs have been collected during four years. The outcome is a rare example of a large scale real-environment speech database. A simulation experiment is carried out with this database to investigate how the system's performance improves during the first two years of operation. The purpose is to determine empirically the amount of real-environment data which has to be prepared to build a system with reasonable speech recognition performance and response accuracy. Furthermore, the relative importance of developing the main system components, i.e. speech recognizer and the response generation module, is assessed. Although depending on the system's modeling capacities and domain complexity, experimental results show that overall performance stagnates after employing about 10-15 k utterances for training the acoustic model, 40-50 k utterances for training the language model and 40 k-50 k utterances for compiling the question and answer database. The Q&A database was most important for improving the system's response accuracy. Finally, the portability of the well-trained first system prototype for a different environment, a local subway station, is investigated. Since collection and preparation of large amounts of real data is impractical in general, only one month of data from the new environment is employed for system adaptation. While the speech recognition component of the first prototype has a high degree of portability, the response accuracy is lower than in the first environment. The main reason is a domain difference between the two systems, since they are installed in different environments. This implicates that it is imperative to take the behavior of users under real conditions into account to build a system with high user satisfaction.

This paper presents methods for detecting transistor short faults using logic level fault simulation and test generation. The paper considers two types of transistor level faults, namely strong shorts and weak shorts, which were introduced in our previous research. These faults are defined based on the values of outputs of faulty gates. The proposed fault simulation and test generation are performed using gate-level tools designed to deal with stuck-at faults, and no transistor-level tools are required. In the test generation process, a circuit is modified by inserting inverters, and a stuck-at test generator is used. The modification of a circuit does not mean a design-for-testability technique, as the modified circuit is used only during the test generation process. Further, generated test patterns are compacted by fault simulation. Also, since the weak short model involves uncertainty in its behavior, we define fault coverage and fault efficiency in three different way, namely, optimistic, pessimistic and probabilistic and assess them. Finally, experimental results for ISCAS benchmark circuits are used to demonstrate the effectiveness of the proposed methods.

This report describes an application of relaxation technique to the alternating direction implicit finite-difference time-domain (ADI-FDTD) method. The ADI-FDTD method is quite stable even when the CFL condition is not satisfied. However, the ADI-FDTD method is computationally more complicate than the conventional FDTD method and this method requires to solving the tri-diagonal matrix equation. Thus, this method may require more computational cost than the standard FDTD method due to the large scale tri-diagonal matrix solution corresponding to a large number of meshes. In this report, relaxation-based solution technique is discussed for the matrix solution and a simple numerical example is shown. As a result, it is confirmed that ADI-FDTD method with the relaxation technique is useful for the acceleration of the electromagnetic field simulation.

In a Cognitive Radio system, it is essential to recognize and avoid sources of interference signals. This paper describes a study on a location sensing scheme for interference signals, which utilizes multi-beam phased array antenna for cognitive wireless networks. This paper also elucidates its estimation accuracy of the interference location for the radio communication link using an OFDM signal such as WiMAX. Furthermore, we use the frequency spectrum of the received OFDM interference signal, to create a method that can estimate the propagation status. This spectrum can be monitored by using a software defined radio receiver.

A novel driving concept, "pulse-width modulation with current uniformization," is proposed for thin-film transistor driven organic light-emitting diode displays (TFT-OLEDs). An example of this driving concept is the combination of "pulse-width modulation with a self-biased inverter" and a "time-ratio grayscale with current uniformization." Its driving operation is confirmed by circuit simulation. It is found that this driving method can compensate the characteristic deviations and degradations of both TFTs and OLEDs and immensely improve luminance uniformity. Finally, its driving operation is also confirmed by an actual pixel equivalent circuit.

A Verilog-AMS model of a fractional-N frequency synthesizer is presented that is capable of predicting spurious tones as well as noise and jitter performance. The model is based on a voltage-domain behavioral simulation. Simulation efficiency is improved by merging the voltage controlled oscillator (VCO) and the frequency divider. Due to the benefits of Verilog-AMS, the ΔΣ modulator which is incorporated in the synthesizer is modeled in a fully digital way. This makes it accurate enough to evaluate how the performance of the frequency synthesizer is affected by cyclic behavior in the ΔΣ modulator. The spur-minimizing effect of an odd initial condition on the first accumulator of the ΔΣ modulator is verified. Sequence length control and its effect on the fractional-N frequency synthesizer are also discussed. The simulated results are in agreement with prior published data on fractional-N synthesizers and with new measurement results.

This paper proposes a soft-error model for accurately estimating reliability of a computer system at the architectural level within reasonable computation time. The architectural-level soft-error model identifies which part of memory modules are utilized temporally and spatially and which single event upsets (SEUs) are critical to the program execution of the computer system at the cycle accurate instruction set simulation (ISS) level. The soft-error model is capable of estimating reliability of a computer system that has several memory hierarchies with it and finding which memory module is vulnerable in the computer system. Reliability estimation helps system designers apply reliable design techniques to vulnerable part of their design. The experimental results have shown that the usage of the soft-error model achieved more accurate reliability estimation than conventional approaches. The experimental results demonstrate that reliability of computer systems depends on not only soft error rates (SERs) of memories but also the behavior of software running in computer systems.