An innovative small planar packaging(SPP)system is described that can be combined with card-on-board(COB)packaging in high-speed asynchronous transfer mode switching systems with throughput of over 40-Gb/s. The SPP system provides high I/O pin count density and high packaging density, combining the advantages of both planar packaging used in computer systems and COB packaging used in telecommunication systems. Using a newly developed quasi-coaxial zero-insertion-force connector, point-to-point 311 Mb/s of 8-bit parallel signal transmission is achieved in an arbitrary location on the SPP systems shelf. Also about 5400 I/O connections in the region of the planar packaging system are made, thus the SPP system effectively eliminates the I/O pin count limitation. Furthermore, the heat flux management capability of the SPP system is five times higher than of conventional COB packaging because of its air flow control structure. An SPP system can easily enlarge the switch throughput and it will be useful for future high-speed, high-throughput ATM switching systems.

Merged DRAM/logic LSIs could provide high on-chip memory bandwidth by interconnecting logic portions and DRAM with wider on-chip buses. For merged DRAM/logic LSIs with the memory hierarchy including cache memory, we can exploit such high on-chip memory bandwidth by means of replacing a whole cache line (or cache block) at a time on cache misses. This approach tends to increase the cache-line size if we attempt to improve the attainable memory bandwidth. Larger cache lines, however, might worsen the system performance if programs running on the LSIs do not have enough spatial locality of references and cache misses frequently take place. This paper describes a novel cache architecture suitable for merged DRAM/logic LSIs, called variable line-size cache or VLS cache, for resolving the above-mentioned dilemma. The VLS cache can make good use of the high on-chip memory bandwidth by means of larger cache lines and, at the same time, alleviate the negative effects of larger cache-line size by partitioning each large cache line into multiple sub-lines and allowing every sub-line to work as an independent cache line. The number of sub-lines involved when a cache replacement occurs can be determined depending on the characteristics of programs. This paper also evaluates the cost/performance improvements attainable by the VLS cache and compares it with those of conventional cache architectures. As a result, it is observed that a VLS cache reduces the average memory-access time by 16. 4% while it increases the hardware cost by only 13%, compared to a conventional direct-mapped cache with fixed 32-byte lines.

In merged DRAM/logic LSIs, it is necessary to reduce the number of DRAM refreshes because of higher heat dissipation caused by the logic portion on the same chip. In order to overcome this problem, we propose several DRAM refresh architectures. The basic is to eliminate unnecessary DRAM refreshes. In addition to this, we propose a method for reducing the number of DRAM refreshes by relocating data. In order to evaluate these architectures and method, we have estimated the DRAM refresh count in executing benchmark programs under several models which simulate each combination of them. As a result, in the most effective combination, we have obtained more than 80% reduction against a conventional DRAM refresh architecture for most of benchmark programs. In addition to it, we have taken normal DRAM access into account, even then we have obtained more than 50% reduction for several benchmarks.

We demonstrate a very simple and compact optical transceiver diode module using a passive alignment on a silicon bench with a V-groove. The excess loss caused by the passive alignment of an optical transceiver diode and a flat-end optical fiber is only 0. 6 dB. A high coupling efficiency of -4. 3 dB is obtained. This results in a high responsivity with a wavelength- and polarization-independence of 0. 5 dB over a 70 nm wavelength range and in good laser performance.

We here consider an extension of the validity of classical criteria ensuring the robustness of the statistical features of discrete time dynamical systems with respect to implementation inaccuracies and noise. The result is achieved by proving that, whenever a discrete time dynamical system is robust, all the discrete time dynamical systems topologically conjugate with it are also robust. In particular, this result offer an explanation for the stochastic robustness of the logistic map, which is confirmed by the reported experimental measurements.

The required building blocks of CMOS fuzzy chips capable of performing as adaptive fuzzy systems are described in this paper. The building blocks are designed with mixed-signal current-mode cells that contain low-resolution A/D and D/A converters based on current mirrors. These cells provide the chip with an analog-digital programming interface. They also perform as computing elements of the fuzzy inference engine that calculate the output signal in either analog or digital formats, thus easing communication of the chip with digital processing environments and analog actuators. Experimental results of a 9-rule prototype integrated in a 2. 4-µm CMOS process are included. It has a digital interface to program the antecedents and consequents and a mixed-signal output interface. The proposed design approach enables the CMOS realization of low-cost and high-inference fuzzy systems able to cope with complex processes through adaptation. This is illustrated with simulated results of an application to the on-line identification of a nonlinear dynamical plant.

This paper is concerned with the validation of simple turning points of two-point boundary value problems of nonlinear ordinary differential equations. Usually it is hard to validate approximate solutions of turning points numerically because of it's singularity. In this paper, it is pointed out that applying the infinite dimensional Krawcyzk-based interval validation method to enlarged system, the existence of simple turning points can be verified. Taking an example, the result of validation is also presented.

Synchronization between two fully stretching piecewise affine Markov maps in the usual master-slave configuration has been proven to be possible in some interesting 2-dimensional and 3-dimensional cases. Aim of this contribution is to make a further step in the study of this phenomenon by showing that, if the two systems synchronize, the probability of having a certain synchronization time is bounded from above by an exponentially vanishing distribution. This result gives some formal ground to the numerical evidence shown in [2].

Simplification orderings, like the recursive path ordering and the improved recursive decomposition ordering, are widely used for proving the termination property of term rewriting systems. The improved recursive decomposition ordering is known as the most powerful simplification ordering. Recently Jouannaud and Rubio extended the recursive path ordering to higher-order rewrite systems by introducing an ordering on type structure. In this paper we extend the improved recursive decomposition ordering for proving termination of higher-order rewrite systems. The key idea of our ordering is a new concept of pseudo-terminal occurrences.

In this paper, a two-dimensional (2-D) binary-valued (BV) lapped transform (LT) is proposed. The proposed LT has basis images which take only BV elements and satisfies the axial-symmetric (AS) property. In one dimension, there is no 2-point LT with the symmetric basis vectors, and the property is achieved only with the non-overlapping basis which the Hadamard transform (HT) has. Hence, in two dimension, there is no 22-point separable ASLT, and only 2-D HT can be the 22-point separable AS orthogonal transform. By taking non-separable BV basis images, this paper shows that a 22-point ASLT can be obtained. Since the proposed LT is similar to HT, it is referred to as the lapped Hadamard transform (LHT). LHT of larger size is shown to be provided with a tree structure. In addition, LHT is shown to be efficiently implemented by a lattice structure.

A password authentication method PERM has been developed for application to e-mail forwarding. This method is suitable for communications in insecure network environments such as the Internet. In particular, it can be adapted to Internet appliances and Java applets which have limited performance. The PERM method does not require password resettings and enables high-speed authentication processing with a small-sized program. Moreover, it does not use facilities or mechanisms for generating random numbers and writing them into and reading them out of an IC card or similar storage medium on the user's side.

An efficient active noise control algorithm based on the lattice-transversal joint (LTJ) filter structure is presented, and applied to the active control of broadband noise in a 3-dimensional enclosure. The presented algorithm implements the filtered-x LMS within the LTJ structure obtained by cascading the lattice and transversal structures. Simulation results show that the LTJ-based noise control algorithm has fast convergence speed that is comparable to the lattice-based algorithm while its computational complexity is less demanding.

In this paper, we extend the Gnaedig's results on termination of order-sorted rewriting. Gnaedig required a condition for order-sorted signatures, called minimality, for the termination proof. We get rid of this restriction by introducing a transformation from a TRS with an arbitrary order-sorted signature to another TRS with a minimal signature, and proving that this transformation preserves termination.

Video-on-Demand (VOD)servers are becoming feasible. These servers are a building component in a heterogeneous multimedia environment but have voluminous data to store and manage. If only disk-based secondary storage systems are used to store and manage this huge amount of data the system cost would be extensively high. A tape-based tertiary storage system seems to be a reasonable solution to lowering the cost of storage and management of this continuous data. However, the usage of a tertiary storage system to store large continuous data introduces several issues. These are mainly the replacement policy on disks, the decomposition and the placement of continuous data chunks on tapes, and the scheduling of multiple requests for materializing objects from tapes to disks. In this paper we address these issues and we propose solutions based on some heuristics we experimented in a simulator.

In this paper, we give a solution to the problem of conflict-free access of various slices of data in parallel processor for image processing. Image processing operations require a memory system that permits parallel and conflict-free access of rows, columns, forward diagonals, backward diagonals, and blocks of two-dimensional image array for an arbitrary location. Linear skewing schemes are useful methods for those requirements, but these schemes require complex Euclidean division by prime number. On the contrary, nonlinear skewing schemes such as XOR-schemes have more advantages than the linear ones in address generation, but these schemes allow conflict-free access of some array slices in restricted region. In this paper, we propose a new XOR-scheme which allows conflict-free access of arbitrarily located various slices of data for image processing, with a two-fold the number of memory modules than that of processing elements. Further, we propose an efficient data alignment network which consists of log N + 2-stage multistage interconnection network utilizing Omega network.

This paper proposes a bitstream scaling technique for MPEG video for the purpose of media synchronizations. The proposed scaling technique can reduce the frame rate as well as the bit rate of an MPEG data sequence to fit them to the values specified by a synchronization system. The advantage of the proposed technique over existing scaling methods is that it is considering not only the performance of synchronization but also the picture quality of the resulting sequences. To further improve the quality of sequences scaled by the proposed method, this paper also proposes an MPEG encoding technique which sets some of the parameters suitable for the scaling. An experiment using these techniques in an actual media synchronization system has illustrated the usefulness of the proposed approach.

High- and low-reflection Bragg gratings with a flat-top spectral response free from ripples are proposed. Add/drop filters are created based on gratings photoinduced on planar waveguides by using the new design schemes. The measured spectral responses for the high and low reflection gratings are in good agreement with the calculated ones, and show the flat-top spectral responses.

In this paper, we study the optimal allocation of multimedia files in distributed network systems. In these systems, the files are shared by users connected with different servers geographically separated, and each file must be stored in at least one of servers. Users can access any files stored in any servers connected with high-speed communication networks. Copies of the files accessed frequently are to be stored in several servers that have databases. So, it is one of the most important problems how to assign the files to servers in view of costs and delays. Considering these problems in heterogeneous network environments, we present a new system model that covers wide range of multimedia network applications like VOD, CALS, and so on. In these systems, it is obvious that there is trading-off relationship between costs and delays. Our objective is to find the optimal file allocation such that the total cost is minimized subject to the total delay. We introduce a 0-1 integer programming formulation for the optimization problem, and find the optimal file allocation by solving these formulae.

This paper is concerned with a concept called universality or completeness of sets of logic devices. Universality characterizes sets of logic devices which can be used for the construction of arbitrary logic circuits. The elemental universality proposed here is the most general condition of universality which covers logic devices with/without delay time and combinational/sequential circuits. The necessary and sufficient condition of elemental universality shows that nonlinearity and nonmonotonicity are essential conditions for the realization of various digital mechanisms.

Evaluating analytically computer architecture performance is mostly cheap and quick. However, existing analytical performance evaluation techniques usually have a difficult and time-consuming modeling process. Moreover, existing techniques do not support well the capability for finding the bottleneck and its cause of a target system being evaluated. To address the above problems and to enhance analytical performance evaluation technology, in this paper we propose a software tool that accepts system models described in a specification language, generating an executable program that performs the actual performance evaluation. The whole approach is built on a subsystem-oriented performance evaluation tool, which is, in turn, based on a formal subsystem-oriented performance evaluation technique and a subsystem specification language.