A direct conversion transmitter IC including a proposed frequency doubler, a quadrature modulator, and a 3-bit variable attenuator was fabricated using BiCMOS technology with fT of 12 GHz. This architecture employing frequency doubler is intended for realizing wireless terminals that are low in cost and small in size. The architecture is effective for reducing serious interference between PA and VCO by making the VCO frequency different from that of PA. The proposed frequency doubler comprises a current-driven 90 phase-shifter and an ECL-EXOR circuit for both low power operation and wide input power range of local oscillator (LO). The proposed frequency doubler keeps high output power even when rectangular wave from LO is applied owing to use of the current-driven 90 phase-shifter instead of a voltage-driven 90 phase-shifter. An LO leakage of less than -25 dBc, an image rejection ratio in excess of 45 dBc, and a maximum attenuation of 21 dB were measured. The transmitter IC successfully operates at LO power above -15 dBm and consumes 68 mA from 2.7 V power supply voltage. An active die size is 1.5 mm3 mm.

The system architectures, which allow a high performance fully balanced (FB) system based on ordinary/modified single-ended opamps to be implemented, are investigated and the basic and general requirements are formulated. Two new methods of an FB analog system design, which contribute towards achieving both a high performance IC system implementation and a great reduction of the design time are presented. It is shown that a single-ended system based on any type of opamp (rail-to-rail, constant gm, etc. ), realized in any technology (CMOS, bipolar, BiCMOS, GaAs), can be easily and effectively converted to its FB counterpart in a very practical way. Using the proposed rules, any FB system implementation with opamps (data converter, modulator, filter, etc. ) requires only a single-ended system version design and the drawbacks related to a conventional FB system design are avoided. The principles of the design are pointed out and they are verified by experimental results.

Lots of self-tuning control schemes have been proposed for tuning the parameters of control systems. Among them, pole-assignment schemes have been widely used for tuning the parameters of control systems with unknown time delays. They are usually classified into two methods, the implicit and the explicit methods according to how to identify the parameters. The latter has an advantage to design a control scheme by taking account of the stability margin and control performance. However, it involves a considerably computational burden to solve a Diophantine equation. A simple scheme is proposed in this paper, which can construct a multivariable self-tuning pole-assignment control system, while taking account of the stability margin and control performance without solving a Diophantine equation.

This letter addresses how to set SIR targets higher than normally required, in order to mitigate the effect of signal-to-interference ratio (SIR) measurement error included in power control steps. We find that scaling up the SIR targets by 1 dB is conformable to resisting SIR measurement error for code division multiple access (CDMA) mobile systems.

This paper gives an overview of research activities on high performance databases in Japan. It focuses on parallel algorithms for relational databases and data mining, parallel approaches for object-oriented databases, and parallel disk systems. Studies surveyed in this paper are carried out mainly by database researchers in Japanese universities under the Grant-in-Aid for Scientific Research (1996-1998).

This paper studies the problem of testing concurrent systems considered as blackboxes and specified using asynchronous Communicating Finite State Machines. We present an approach to derive test cases for concurrent systems in a succinct and formal way. The approach addresses the state space explosion problem by introducing a causality relation model and the concept of logical time to express true concurrency and describe timing constraints on events. The conformance relation between test cases and trace observed from the real system is defined, and a new test architecture as well as a test case application is presented according to the conformance relation defined. To improve verdict capability of test cases, the approach is enhanced by relaxing the unit-time assumption to any natural number. And a computationally efficient algorithm for the enhanced approach is presented and the algorithm is evaluated in terms of computational efficiency and verdict capability. Finally the approach is generalized to describe timing constraints by any real numbers.

Recently the study and implementation of elliptic curve cryptosystems (ECC) have developed rapidly and its achievements have become a center of attraction. ECC has the advantage of high-speed processing in software even on restricted environments such as smart cards. In this paper, we concentrate on complete software implementation of ECC over a prime field on a 16-bit microcomputer M16C (10 MHz). We propose a new type of prime characteristic of base field suitable for small and fast implementation, and also improve basic elliptic arithmetic formulas. We report a small and fast software implementation of a cryptographic library which supports 160-bit elliptic curve DSA (ECDSA) signature generation, verification and SHA-1 on the processor. This library also includes general integer arithmetic routines for applicability to other cryptographic algorithms. We successfully implemented the library in 4 Kbyte code/data size including SHA-1, and confirmed a speed of 150 msec for generating an ECDSA signature and 630 msec for verifying an ECDSA signature on M16C.

Detecting security flaws is important in order to keep the database secure. A security flaw in object-oriented databases means that a user can infer the result of an unpermitted method only from permitted methods. Although a database management system enforces access control by an authorization, security flaws can occur under the authorization. The main aim of this paper is to show an efficient decision algorithm for detecting a security flaw under a given authorization. This problem is solvable in polynomial time in practical cases by reducing it to the congruence closure problem. This paper also mentions the problem of finding a maximal subset of a given authorization under which no security flaw exists.

For advanced data-oriented applications in distributed environments, effective information is frequently obtained by integrating or merging various autonomous information sources. There are many problems: how to search information sources, how to resolve their heterogeneity, how to merge or integrate target sources, how to represent information sources with a common protocol, and how to process queries. We have proposed a new language, QUIK, as an extension of a deductive object-oriented database (DOOD) language, QUIXOTE, and extend typical mediator systems. In this paper, we discuss various features of QUIK: programming capabilities as integrating an exchange model and mediator specifications, merging subsumption relations for maintaining consistency, searching alternative information sources by hypothesis generation, and identifying objects.

This paper surveys recent research activities on three major areas of digital media information base, namely, video database systems as a typical example of temporal application, database systems for mixed reality as an instance of spatial application, and kansei management for digital media retrieval as a case of humanistic feelings application. Current research results by the project Advanced Database Systems for Integration of Media and User Environments are reported.

This study presents a method that can be used to manage individual pieces of information in large scale distributed geographic information systems (GIS). In a distributed GIS, ordinary users usually cannot alter any of the contents on the server. The method in this study can be used to alter the content or add individual datums onto these types of non-write-permitted data sets. The authors have called it a 'Geographic Differential Script File' (GDSF). A client creates a GDSF, which contains private information that is to be added onto the served data. The client keeps this file on a local disk. When the user employs the data, he applies the differential script sequence onto the downloaded data in order to retrieve the information. GDSF is a collection of graphic operation commands which insert and delete objects as well as modify operations. GDSF also contains modifications of the attribute information of geographic entities. This method can also be used to revise information that is published on ROM media, e. g. CD-ROM or DVD-ROM, as well as in a distributed environment. In this paper, the method and results of applying it are presented.

In this paper a high-performance copy network named PPCN is proposed for large scale ATM switching systems. The proposed copy network consists of multiple planes of the P2I Copy Networks(PCN) arranged in parallel. The PCN planes are designed based on the P2I multistage interconnection networks (MINs). A single PCN plane is itself a preliminary self-routing copy network which, however, is not a non-blocking one. A novel dispatcher is designed to dispatch input cells to the PCN planes such that no internal blocking nor output contention arises during the cell replication procedure and the offered load can be shared in an efficient way. The architecture of the PPCN provides flexibility for the maximum fanout for an input cells. In a PPCN system, the maximum fanout for an input cells is determined only by the number of interconnection stages within the PCN planes, independent of the input size of the system. The performance of the PPCN is studied under uniform traffic. It is shown that a small constant number of PCN planes are sufficient for a PPCN system to achieve an acceptable low overflow probability regardless of the system size. The hardware complexity of an N N PPCN is O(N log2 K) and the length of the routing tag is O(log2 K) bits, where K is the maximum fanout for an input cell. The storage complexity of the translation tables adopted in an N-inlet PPCN is O(N), which is much lower than that of the previously proposed ones.

There is increasing demand for corporate information systems that have a simple human interface and are easy to access via WWW browsers. This paper proposes WebBASE, which integrates the WWW and relational databases. Experimental evaluation shows that WebBASE offers superior performance compared to existing products. Field studies of actual WebBASE applications show that it can improve the productivity of software developers for intranet application development.

We introduce an ontology for transportation systems demand forecasting and its implementation into a decision support system (DSS) generator. The term ontology, as we use it here, means a collection of building blocks necessary and sufficient to construct a skeleton of a specific DSS, that is a task ontology. The ontology is specified in constraint logic, which also ensures a good support for modularity.

In this paper, we propose a test methodology for core-based system LSIs. Our test methodology aims to decrease testing time for core-based system LSIs. In our method, every core is supplied with several sets of test vectors. Every set of test vectors guarantees sufficient fault coverage. Each set of test vectors consists of two parts. One is based on built-in self-test (BIST) and the other is based on external testing. These sets of test vectors are designed to have different ratio of BIST to external testing each other for every core. We can minimize testing time for core-based system LSIs by selecting from the given sets of test vectors for each core. The main contributions of this paper are summarized as follows. (i) BIST is efficiently combined with external testing to relax the limitation of the external primary inputs and outputs. (ii) External testing for one of cores and BISTs for the others are performed in parallel to reduce the total testing time. (iii) The testing time minimization problem for core-based system LSIs is formulated as a combinatorial optimization problem to select the optimal set of test vectors from given sets of test vectors for each core.

We describe a new multiport memory which is called Shared DRAM (SHDRAM) to overcome bus-bottle neck problem in parallel processor system with shared memory. The processors are directly connected to this SHDRAM without conventional common bus. The test chip with 32 kbit memory cells is fabricated using a 1. 5 µm CMOS technology. The basic operation is confirmed by the circuit simulation and experimental results. In addition, it is confirmed by the computer simulation that the system performance with SHDRAM is superior to that with conventional common buses.

A double-layer Associative Memory System (AMS) based on the Cerebella Model Articulation Controller (CMAC) (CMAC-AMS), owing to its advantages of simple structures, fast searching procedures and strong mapping capability between multidimensional input/output vectors, has been successfully used in such applications as real-time intelligent control, signal processing and pattern recognition. However, it is still suffering from its requirement for a large memory size and relatively low precision. Furthermore, the hash code used in its addressing mechanism for memory size reduction can cause a data-collision problem. In this paper, a new high-order Associative Memory System based on the Newton's forward interpolation formula (NFI-AMS) is proposed. The NFI-AMS is capable of implementing high-precision approximation to multivariable functions with arbitrarily given sampling data. A learning algorithm and a convergence theorem of the NFI-AMS are proposed. The network structure and the scheme of its learning algorithm reveal that the NFI-AMS has advantages over the conventional CMAC-type AMS in terms of high precision of learning, much less required memory size without the data-collision problem, and also has advantages over the multilayer Back Propagation (BP) neural networks in terms of much less computational effort for learning and fast convergence rate. Numerical simulations verify these advantages. The proposed NFI-AMS, therefore, has potential in many application areas as a new kind of associative memory system.

The datapath width of a core processor has a strong effect on cost, power consumption, and performance of an embedded system integrated with memories into a single-chip. However, it is difficult for designers to appropriately determine the datapath width for each application because of the limited reusability of software and the lack of compilation techniques. The purpose of this paper is to clarify supports required from software for the optimal datapath width determination. As a solution, an embedded programming language, called Valen-C, and a retargetable Valen-C compiler are proposed. In this paper, the syntax and semantics of Valen-C along with the mechanism of the Valen-C retargetable compiler and how to preserve the accuracy of computation of programs in relation to various datapath widths are also described. Experiments with practical applications show that the total cost of the system including a core processor, ROM, and RAM is drastically reduced with little performance loss by reducing the datapath width.

This paper proposes a method to reduce the context switching time using a register bank to store contexts of working tasks. Hardware cost and performance were measured by modeling the register bank and controller in VHDL. Following results were obtained: (1) The controller can be implemented with a much smaller amount of hardware cost compared to that of the register bank, which is realized by SRAM module. (2) Context switching time can be reduced to less than 50% compared to that by software implementation. (3) Combination of the proposed architecture with our previous work (RTOS implemented in HW) gives us much higher performance of a hard real-time system.

A fractal image coding scheme using classified range regions is proposed. Two classes of range regions, shade and nonshade, are defined here, A shade range region is encoded by the average gray level, while a nonshade range region is encoded by IFS parameters. To obtain classified range regions, the two-stage block merging scheme is proposed. Each range region is produced by merging primitive square blocks. Shade range regions are obtained at the first stage, and from the rest of primitive blocks nonshade range regions are obtained at the second stage. Furthermore, for increasing the variety of region shape, the 8-directional block merging scheme is defined by extension of the 4-directional scheme. Also, two similar schemes for encoding region shapes, each corresponding to the 4-directional block merging scheme and the 8-directional block merging scheme, are proposed. From the results of simulation by using a test image, it was demonstrated that the variety of region shape allows large shade range regions to be extracted efficiently, and these large shade range regions are more effective in reduction of total amount of codebits with less increase of degradation of reconstructed image quality than large nonshade range regions. The 8-directional merging and coding scheme and the 4-directional scheme reveal almost the same coding performance, which is improved than that of the quad-tree partitioning scheme. Also, these two schemes achieve almost the same reconstructed image quality.