This paper deals with a method of estimating the parameters and the order of a linear system using differential digital filters and the resultant. From the observed signals of the input and output of an objective system, we extract the differential signals from the zero order to an appropriate high order with the same phase characteristics, using several digital filters. On the assumption that the system order is known, we estimate the parameters of the transfer function and evaluate the estimation error bounds. We propose a criterion function generated by the product of the highest order coefficients and the resultant of the numerator and denominator of the estimated transfer function. Applying this criterion function, we can estimate the order of the objective system. The threshold corresponding to this criterion function is evaluated from the deviation in the frequency characteristics of the used differential filters and the error bound of the estimated parameters. In order to demonstrate the propriety of the proposed method, some numerical simulations are presented.

A compact residue arithmetic multiplier based on the radix-4 signed-digit arithmetic is presented. Conventional residue arithmetic circuits have been designed using binary number arithmetic system, but the carry propagation arises which limits the speed of arithmetic operations in residue modules. In this paper, two radix-4 signed-digit (SD) number representations, {-2,-1,0,1,2} and {-3,-2,-1,0,1,2,3}, are introduced. The former is used for the input and output, and the later for the inner arithmetic circuit of the presented multiplier. Integers 4p and 4p 1 are used as moduli of residue number system (RNS), where p is a positive integer and both circuits for partial product generation and sum of the partial products can be efficiently constructed by using the multiple-valued current-mode circuits. The modulo m addition, m=4p or m=4p 1, can be performed by an SD adder or an end-around-carry SD adder with the multiple-valued circuits and the addition time is independent of the word length of operands. The modulo m multiplier can be compactly constructed using a binary tree of the multiple-valued modulo m SD adders, and consequently the modulo m multiplication is performed in O(log p) time. The number of MOS transistors required in the presented residue arithmetic multiplier is about 86p2 + 66p.

We report relations between invariant manifolds of saddle orbits (Lyapunov family) around a saddle-center equilibrium point and lowest periodic orbits on the two degree of freedom swing equation system. The system consists of two generators operating onto an infinite bus. In this system, a stable equilibrium point represents the normal operation state, and to understand its basin structure is important in connection with practical situations. The Lyapunov families appear under conservative conditions and their invariant manifolds constitute separatrices between trapped and divergent motions. These separatrices continuously deform and become basin boundaries, if changing the system to dissipative one, so that to investigate those manifolds is meaningful. While, in the field of two degree of freedom motions, systems with saddle loops to a saddle-center are well studied, and existence of transverse homoclinic structure of separatrix manifolds is reported. However our investigating system has no such loops. It is interesting what separatrix structure exists without trivial saddle loops. In this report, we focus on above invariant manifolds and lowest periodic orbits which are foliated for the Hamiltonian level.

This paper treats the systematic design of chaos generators which are capable of generating continuous-time signals with prescribed probability density function and power density spectra. For a specific signal model a statistical analysis is performed such that the inverse problem, i. e. the calculation of the model parameters from prescribed signal characteristics, can be solved. Finally from the obtained model parameters and the model structure the signal generating system is constructed. The approach is illustrated by several examples.

A review of research, covering about 50 years, about random phenomena in nonlinear dynamical systems and the problems of modeling such phenomena using real (as contrasted to abstract, axiomatic) mathematics. Private views of the author concerning personalities and events.

In this paper, we present the theoretical development to stabilize a class of uncertain time-delay system. The system under consideration is described in state space model containing distributed delay, uncertain parameters and disturbance. The main idea is to transform the system state into an equivalent one, which is easier to analyze its behavior and stability. Then, a computational method of robust controller design is presented in two parts. The first part is based on solving a Riccati equation arising in the optimal control theory. In the second part, the finite dimensional Lyapunov min-max approach is employed to cope with the uncertainties. Finally, we show how the resulting control law ensures asymptotic stability of the overall system.

This paper presents a new number representation called the Signed-Weight (SW) number system, which is useful for designing configurable counter-tree architectures for digital signal processing applications. The SW number system allows the unified manipulation of positive and negative numbers in arithmetic circuits by adjusting the signs assigned to individual digit positions. This makes possible the construction of highly regular arithmetic circuits without introducing irregular arithmetic operations, such as negation and sign extension in the two's complement representation. This paper also presents the design of a Field-Programmable Digital Filter (FPDF) architecture--a special-purpose FPGA architecture for high-speed FIR filtering--using the proposed SW arithmetic system.

The aim of this contribution is to take a further step in the study of the impact of chaos-based techniques on classical DS-CDMA systems. The problem addressed here is the sequence phase acquisition and tracking which is needed to synchronize the spreading and despreading sequences of each link. An acquisition mechanism is considered and analyzed in depth to identify analytical expressions of suitable system performance parameters, namely outage probability, link startup delay and expected time to service. Special chaotic maps are considered to show that the choice of spreading sequences can be optimized to accelerate and improve the spreading codes acquisition phase.

This paper proposes applications of a code-division multiplexing technique to VLSI systems free from interconnection problems. We employ a pseudo-random orthogonal m-sequence carrier as a multiplexable information carrier to achieve efficient data transmission. Using orthogonal property of m-sequences, we can multiplex several computational activities into a single circuit, and execute in parallel using multiplexed data transmission with reduced interconnection. Also, randomness of m-sequences offers the high tolerance to interference (jamming), and suppression of dynamic range of signals while maintaining a sufficient signal-to-noise ratio (SNR). We demonstrate application examples of multiplex computing circuits, neural networks, and spread-spectrum image processing to show the advantages.

We developed an optical transceiver diode (TRAD) module for bi-directional time-compression-multiplexing (TCM) transmission systems. A wavelength-insensitive structure as a receiver and a low-capacitance configuration in the module provide a high sensitivity. Stable switching of 156 Mbit/s NRZ burst signals between the transmitter and receiver modes is achieved. In addition, it is shown that optical module cost can be further reduced by using passive alignment on a Si bench.

Two classes of nonlinear feedforward logic (NLFFL) pseudonoise (PN) code generators based on the use of AND and majority logic (ML) gates are compared. Cross-correlation and code-division multiple-access (CDMA) properties of properly designed NLFFL sequences are found to be comparable with the properties of well-known linear PN codes. It is determined that code design employing ML gates with an odd number of inputs is easier compared with designing with AND gates. This is especially true when the degree of nonlinearity is large, since the nonbalance problem, e. g. , at the output of an AND gate, can be avoided. ML type sequences are less vulnerable to correlation attack and jamming by the m-sequence of an NLFFL generator

Minimizing the guard time, Tguard, in the TCM-TDMA PDS scheme is essential in maximizing TCM transmission efficiency. As a replacement for the commonly adopted worst-case approach to TCM-TDMA PDS system estimation, this paper proposes a statistical approach. The level distributions of losses and n-th order Fresnel reflections are determined from published measurements. The proposed approach estimates the reflection of the optical access network.

We developed an optical transceiver diode (TRAD) module for bi-directional time-compression-multiplexing (TCM) transmission systems. A wavelength-insensitive structure as a receiver and a low-capacitance configuration in the module provide a high sensitivity. Stable switching of 156 Mbit/s NRZ burst signals between the transmitter and receiver modes is achieved. In addition, it is shown that optical module cost can be further reduced by using passive alignment on a Si bench.

Petri net is a graphical and mathematical modeling tool for discrete event systems. This paper treats analysis problems of time Petri nets. In this model, a minimal and a maximal firing delays are assigned to each transition. If a transition is 'enabled' it can fire after minimal delay has passed and must fire before maximal delay has elapsed. Since time Petri net can simulate register machines, it has equivalent modeling power to that of Turing machine. It means, however, that most of the analysis problems of time Petri nets with general net structures are undecidable. In this paper, net structures are restricted to a subclass called partially ordered condition (POC) nets and dissynchronous choice (DC) nets. Firing delays are also restricted to satisfy 'static fair condition' which assures chance to fire for all transitions enabled simultaneously. First, a sufficient condition of liveness of time POC net with the static fair condition is derived. Then it is shown that liveness of time DC net with static fair condition is equivalent to liveness of the underlying nontime net. This means that liveness problem of this class is decidable. Lastly, liveness problem of extended free choice (EFC) net is shown to be decidable.

We propose manifold piecewise constant systems (ab. MPC) and consider basic phenomena: the 2-D, 3-D and 4-D MPCs exhibit limit-cycle, line-expanding chaos and area-expanding chaos, respectively. The righthand side of the state equation is piecewise-constant, hence the system dynamics can be simplified into a piecewise-linear return map which can be expressed explicitly. In order to analyze the piecewise-linear return map, we introduce an evaluation function for the piecewise-linear return map and give theoretical evidence for chaos generation. Also the chaotic behaviors are demonstrated in the laboratory.

In this paper, we propose a new structure of blind equalizer and its cost function. The proposed cost function is a quadratic form and has the unique solution. In addition, the proposed scheme can employ iterative algorithms which achieve less computational complexity and can be easily realized in real time processing. In order to verify the effectiveness of the proposed schemes, several computer simulations including a 64-QAM signal equalization have been shown.

A clock recovery circuit is a key component in optical communication systems. In this paper, an optoelectronic clock recovery circuit is reported that monolithically integrates a resonant tunneling diode (RTD) and a uni-traveling-carrier photodiode (UTC-PD). The circuit is an injection-locked-type RTD oscillator that uses the photo-current generated by the UTC-PD. Fundamental and sub-harmonic clock extraction is confirmed for the first time with good clock recovery circuit characteristics. The IC extracts an electrical 11.55-GHz clock signal from 11.55-Gbit/s RZ optical data streams with the wide locking range of 450 MHz and low power dissipation of 1.3 mW. Furthermore, the extraction of a sub-harmonic clock from 23.1-Gbit/s and 46.2-Gbit/s input data streams is also confirmed in the wider locking range of 600 MHz. The RMS jitter as determined from a single sideband phase noise measurement is extremely low at less than 200 fs in both cases of clock and sub-harmonic clock extraction. To our knowledge, the product of the output power and operating frequency of the circuit is the highest ever reported for injection-locked-type RTD oscillators. These characteristics indicate the feasibility of the optoelectronic clock recovery circuit for use in future ultra-high-speed fully monolithic receivers.

This paper is concerned with blind identification of a nonminimum phase transfer function model. By over-sampling the output at a higher rate than the input, it is shown that its input-output relation can be described by a single input multiple output model (SIMO) with a common denominator polynomial. Based on the model expression, we present an algorithm to estimate numerator polynomials and common denominator polynomial in a blind manner. Furthermore, identifiability of the proposed scheme is clarified, and some numerical results are given for demonstrating its effectiveness.

A clock recovery circuit is a key component in optical communication systems. In this paper, an optoelectronic clock recovery circuit is reported that monolithically integrates a resonant tunneling diode (RTD) and a uni-traveling-carrier photodiode (UTC-PD). The circuit is an injection-locked-type RTD oscillator that uses the photo-current generated by the UTC-PD. Fundamental and sub-harmonic clock extraction is confirmed for the first time with good clock recovery circuit characteristics. The IC extracts an electrical 11.55-GHz clock signal from 11.55-Gbit/s RZ optical data streams with the wide locking range of 450 MHz and low power dissipation of 1.3 mW. Furthermore, the extraction of a sub-harmonic clock from 23.1-Gbit/s and 46.2-Gbit/s input data streams is also confirmed in the wider locking range of 600 MHz. The RMS jitter as determined from a single sideband phase noise measurement is extremely low at less than 200 fs in both cases of clock and sub-harmonic clock extraction. To our knowledge, the product of the output power and operating frequency of the circuit is the highest ever reported for injection-locked-type RTD oscillators. These characteristics indicate the feasibility of the optoelectronic clock recovery circuit for use in future ultra-high-speed fully monolithic receivers.

This paper presents a novel dead-beat synchronization scheme and applies it to communications in discrete-time chaotic systems. A well-known Henon system is considered as an illustrative example. In addition, a Henon-based image processing application effectively exploits the proposed scheme's effectiveness.