Methods usually employed for carrying out division in logic are based on algebraic or Boolean techniques. Algebraic division is fast but results may be less than optimal. Boolean division will yield better results but generally it is much slower because a minimization step is required. In [4], Kim and Dietmeyer proposed a new type of division, called extended algebraic division, and described a heuristic algorithm for it. A feature is that, unlike Boolean division, it does not require a minimization step. The present paper is concerned with an efficient algorithm for exact extended algebraic division. The algorithm was developed within the SIS environment, a program for logic synthesis developed at U.C. Berkeley. Experiments on factoring PLA's demonstrate a significant improvement in quality with a reasonable increase in run time.

Scanning near-field optical microscopy (SNOM) combined with Kelvin force microscopy (KFM) using a microfabricated force-sensing cantilever with a lead zirconate titanate (PZT) thin film as an integrated deflection sensor have been developed. We applied the frequency modulation (FM) detection method to this setup to increase the detection sensitivity of electrostatic forces between a probe tip and a sample. Latex particles dispersed in a polyvinylalcohol (PVA) thin film deposited onto a glass substrate were stably imaged with the SNOM while both local optical and electrical properties of a ferroelectric thin film were successfully investigated.

Partition chains with balanced vectors are constructed in this paper. The partition chains can be constructed from weight distribution of Reed-Muller codes or randomization lemma. For the partition chain, its line coding parameters such as maximum runlength and running digital sum are obtained. The trellis and multilevel code structure can be used to design the error-correcting balanced codes. Especially, by adopting balanced trellis codes as constituent codes, balanced turbo codes can be designed. As results, the designed error-correcting balanced codes have good coding parameters.

A novel multilevel construction for permutation codes is presented. A permutation code of length n is a subset of all the vectors obtained from coordinate permutations on the vector (0,1,. . . ,n-1). We would like to construct a permutation code with cardinality as large as possible for a given code length n and a minimum distance. The proposed construction is available when n = 2m (m is a positive integer). We exploit m-constant weight binary codes as component codes and combine them in a multilevel way. Permutation codes with various parameters can be constructed by selecting appropriate combination of component codes. Furthermore, multi-stage decoding is available for decoding the permutation codes constructed by the proposed construction.

Reliability-based decoding algorithm in multistage decoding of multilevel codes is discussed. Through theoretical analyses, effects of soft reliability information are examined for different types of partitionings.

In this letter, a new scheme of designing multilevel BTC coding is proposed. The optimal quantization can obtain by selecting the quantization threshold with an exhaustive search. However, it requires an enormous amount of computation and is thus impractical while we take an exhaustive search for the multilevel BTC. A two-steps searching method is applied to reduce the computational complexity. Comparisons of results with various methods have verified that the proposed method approach to the optimal quantization with little computation complexity.

This paper reviews device technologies of flash memories, whose market has grown explosively due to the advantages of: (1) their low cost provided by availability of the single-transistor type cell with adoption of block-erase operation; (2) high functionality as electrically erasable and programmable non-volatile memories; and (3) high reliability with the mature floating gate technology. As for fast-random-access flash memories, their scaling issue, including a multi-level-cell technology, is discussed, and technologies for low power consumption, which is highly demanded for mobile electronic equipment, their major application, are described. Furthermore, device technologies of serial-access flash memories, which have achieved low cost with cell-size reduction, are also reviewed. Finally, a future promising technology of the NROM concept, which achieves a multi-storage-cell with low voltage operation and a simple process, is introduced.

A chain ferroelectric random-access memory (chain FeRAM) is a solution for future high-density and high-speed nonvolatile memory. One memory cell consists of one transistor and one ferroelectric capacitor connected in parallel, and one memory cell block consists of plural cells and a block selecting transistor in series. This configuration realizes small memory cell of 4F2 size and fast random access time. This paper shows an overview and trend of chain FeRAM architecture. First, the concept of chain FeRAM is presented, and basic operations including two cell-plate driving schemes are discussed. Second, assuming multi-megabit generation, ideal features and performances are discussed in terms of die size, speed and other aspects. Third, the prototype of chain FeRAM and the practical cell structure for megabit-scale memories using 0.5 µ m 2-metal CMOS process are demonstrated. By introducing fast and compact cell-plate drive technique, this prototype achieves random access time of 37-ns and read/write cycle time of 80-ns, which are the fastest speeds reported for FeRAMs. Fourth, after discussing future memory cell trend and problems respecting scaled FeRAMs, a gain cell block approach for future gigabit-scale chain FeRAMs is introduced. This realizes both a small average cell size and a large cell signal even at small cell polarization.

Effects of imprint on signal margin in FeRAM with Pt/SrBi2Ta2O9/Pt capacitors have been investigated. Imprint, induced during high temperature storage, significantly reduced the signal margin and hence determines lifetime of FeRAM. Initial signal margin of 470 mV is reduced to 290 mV after storage at 175C for 96 hours. From the reduction rate of the signal margin, it is estimated that imprint lifetime of the FeRAM is more than 10 years even though the storage temperature is 175C.

We have manufactured large-scaled highly reliable MNOS EEPROMs over the last twenty years. In particular, at the present time, the smart-card microcontroller incorporating an embedded 32-kB MNOS EEPROM is rapidly expanding the markets for mobile applications. It might be said that we have established the conventional MNOS nonvolatile semiconductor memory technology. This paper describes the device design concepts of the MNOS memory, which include the optimization and control of the tunnel oxide film thickness (1.8 nm), and the scaling guideline that considers the charge distribution in the trapping nitride film. We have developed a high-performance MONOS structure and have not found any failure due to the MONOS devices in high-density EEPROM products during 10-year data retention tests after 105 erase/write cycles. The future development of this highly reliable MNOS-type memory will be focussed on the high-density cell structure and high-speed programming method. Recently, some promising ideas for utilizing an MNOS-type memory device, such as 1-Tr/bit cell for byte-erasable full-featured EEPROMs and 2-bit/Tr cell for flash EEPROMs have been proposed. We are convinced that MNOS technology will advance into the area of nonvolatile semiconductor memories because of its high reliability and high yield of products.

Multilayer feedforward neural network (MFNN) trained by the backpropagation (BP) algorithm is one of the most significant models in artificial neural networks. MFNNs have been used in many areas of signal and image processing due to high applicability. Although they have been implemented as analog, mixed analog-digital and fully digital VLSI circuits, it is still difficult to realize their hardware implementation with the BP learning function efficiently. This paper describes a special BP algorithm for the logic oriented neural network (LOGO-NN) which we have proposed as a sort of MFNN with quantized weights and multilevel threshold neurons. Both weights and neuron outputs are quantized to integer values in LOGO-NNs. Furthermore, the proposed BP algorithm can reduce high precise calculations. Therefore, it is expected that LOGO-NNs with BP learning can be more effectively implemented as digital type circuits than the common MFNNs with the classical BP. Finally, it is shown by simulations that the proposed BP algorithm for LOGO-NNs has good performance in terms of the convergence rate, convergence speed and generalization capability.

Channel coding for bandwidth limited channels based on multilevel bit-interleaved channels is discussed in this paper. This coding and decoding structure has the advantage of simplified design, and naturally incorporates flexible and powerful design of unequal error protection (UEP) capabilities, especially over time-varying channels to be often found in mobile radio communications. Multilevel coded modulation with multistage decoding, and bit-interleaved coded modulation are special cases of the proposed general framework. Simulation results verify the usefulness of the system considered.

DC-free error-correcting codes based on partition chain are presented in this paper. The partition chain can be constructed from code partition chain of Reed-Muller codes. The line coding parameters for the partition chain such as maximum runlength and running digital sum are obtained. The trellis and multilevel code structure can be used to design the DC-free error-correcting codes. Especially, by adopting DC-free trellis codes as constituent codes, DC-free turbo codes can be designed. As results, the presented DC-free error-correcting codes have good coding characteristics.

In this paper, we investigate multilevel coding and multistage decoding for satellite broadcasting with moderate decoding complexity. An unconventional signal set partitioning is used to achieve unequal error protection capabilities. Two possibilities are shown and analyzed for practical systems: (i) linear block component codes with near optimum decoding, (ii) punctured convolutional component codes with a common trellis structure.

While the secure concurrency controllers (SCCs) in multilevel secure database systems (MLS/DBMSs) synchronize transactions cleared at different security levels, they must consider the problem of covert channel. We propose a new SCC, named Verified Order-based secure concurrency controller (VO) that founds on multiversion database. VO maintains elaborated information about ordering relationships among transactions in a way of actively investigating and renewing the ordering relationships whenever it receives operations. With the elaborated information, it becomes capable of aborting transactions selectively whose non-interfered executions definitely violate one-copy serializability and providing more recent data versions to read requests than the other multiversion-based SCCs. Therefore, it comes to reduce the abort ratio and provide data versions of improved trustworthiness to transactions. By virtue of the elaborated information, moreover, VO is able to distinguish worthful versions and worthful transactions from worthless ones, so that it is capable lightening the burdens of maintaining multiple versions and accumulated transaction ordering relationships. For the aborts that are inevitable for preserving one-copy serializability, VO achieves security by deriving the conflicts to occur between transactions that have been cleared at the same security level.

When a micromachine works inside a narrow space inside tubes and equipment such as a microfactory, a microdevice that has a visual function is indispensable. To monitor the minute shapes of microfabrication and microassembly process that are impossible to observe, fiber-optic sensors and actuators for environmental recognition devices have been developed. The devices are designed to allow stereoscopic and microscopic observation and to measure the dimensions of microparts. To achieve these goals and to realize minute structures and functions, we developed environmental recognition devices for microfabrication process with functions of far and near field observation, tactile sensing and tip articulation, for microassembly process with functions of stereoscopic observation and tip articulation. The results show that easy and safe environmental recognition is possible in the narrow spaces of a microfactory.

In this paper, a new scheme for designing multilevel BTC coding is proposed. Optimal quantization can be obtained by selecting the quantization threshold with an exhaustive search. However, this requires an enormous amount of computation and is, thus impractical when we consider an exhaustive search for the multilevel BTC. In order to find a better threshold so that the average mean square error between the original and reconstructed images is a minimum, the genetic algorithm is applied. Comparison of the results of the proposed method with the exhaustive search reveal that the former method can almost achieve optimal quantization with much less computation than that required in the latter case.

For the purpose of realizing a new intelligent system and its simplified VLSI implementation, we propose a new nonvolatile analog memory called "switched diffusion analog memory with feedback circuit (FBSDAM). " FBSDAM has linear writing and erasing characteristics. Therefore, FBSDAM is useful for memorizing an analog value exactly. We also propose a new analog content-addressable memory (CAM) which has neural-like learning and discriminating functions which discriminate whether an incoming pattern is an unknown pattern or a stored pattern. We design and fabricate the CAM using FBSDAM by means of the 4µm double-poly single-metal CMOS process and nonvolatile analog memory technology which are developed by us. The chip size is 3.1 mm3.1 mm. We estimate that the CAM is composed of 50 times fewer transistors and requires 70 times fewer calculation steps than a typical digital computer implemented using similar technology.

This paper proposes Emergent Behavior Based Architecture (EBBA) that fusions heterogeneous sensor information at the level of behavior modules. The characteristics of EBBA are as follows. i) sensor based architecture, ii) constructed by a set of concurrently executable behavior modules, iii) to have multiple methods to achieve given tasks by utilizing behavior modules, iv) a planner can control emergent behaviors. We also have developed mobile robot navigation system based on EBBA and confirmed the efficiency by experiments in the various situations.

In multilevel block modulation codes for QPSK and 8-PSK modulation, a construction of binary component codes is given. These codes have a good minimum Euclidean distance by using different forms of the dependency properties of the binary component codes. Interdependency among component codes is formed by using the binary component subcodes which are derived by the coset decomposition of the binary component codes. The algebraic structures of the codes are investigated to find out how interdependency among component codes gives a good minimum Euclidean distance. First, it is shown that cyclic codes over ZM for M-PSK (M=4,8), where the coding scheme is given by Piret, can be constructed by forming specific interdependency among binary component codes for proposed multilevel coding method. Furthermore, it is shown that better minimum Euclidean distance than above can be obtained by modifying the composition of interdependency among binary component codes. These proposed multilevel codes have algebraic structure of additive group and cyclic property over GF(M). Finally, error performances are compared with those of some code's reference modulation scheme for transmitting the same number of information bits.