An improved numerical computation model is presented to calculate the metal-ferroelectric-semiconductor field effect transistor (MFSFET) characteristics with a sufficiently large gate area which can be applied for large drain voltages. In the presented model, the polarization of the ferroelectric gate insulator is inhomogeneous and treated as a variable along the channel. We have calculated electrical properties of SrBi2Ta2O9/Si MFSFETs and demonstrate that the conventional model, in which the polarization of the ferroelectric gate insulator (Pd) is treated as a constant, overestimate the drain current when the drain voltage is large. In addition, effects of the ratio of remanent polarization to spontaneous polarization (Pr/Ps ratio) of the ferroelectric film on the transistor characteristics are discussed.

A two stage Combline Bandpass Filter (C-BPF) of the Vertically Installed Planar (VIP) structure has been investigated, which is essentially composed of a strongly coupled microstrip lines terminated with a planar fin and through-hole combined with the tapping feed approach. The principle and performance of this filter is studied approximately by an equivalent circuit model and also by the normalized 3D-FDTD method more exactly. The time domain iteration in the FDTD analysis is performed in an expanded time dimension resulting in a reduced CPU time. Some of the obtained numerical results are compared well with the measured ones. A modified VIP combline BPF has the advantages of simple structure, easy tuning, low cost, versatile bandwidth control and good skirt characteristics brought about by two attenuation poles.

We have constructed Bi based layer structured ferroelectric films and their superlattices by a pulsed laser deposition technique. The dielectric constants along c-axis increase with increasing of the number of pseudo-perovskite layers between double Bi2O2 layers. Ferroelectricity appears along the c-axis direction only for the odd number of the perovskite layers owing to the mirror symmetry in a crystal structure. Especially, the Bi2VO5. 5 film shows an atomically flat surface, low dielectric constant of 30 and ferroelectricity of Pr=3 µC/cm2 and Ec=16 kV/cm, respectively. This material is expected to the application for FRAMs.

A review of fundamental and practical limitations on ferroelectric thin-film non-volatile random access memories is given. Size effects are considered (both thickness and lateral dimensions) from the point of view of both depolarization field instabilities and electrical breakdown mechanisms. Emphasis is on switched-capacitor pass-gate architectures, but true ferroelectric FETs (in which the metal gate in the field-effect transistor is replaced with a ferroelectric film) are discussed briefly. The conclusion is that ferroelectric non-volatile RAMs of Gigabit densities are technically viable in the immediate future.

Ferroelectric non-volatile memory (FeRAM) has been inspiring interests since bismuth layer perovskite material family was found to provide "Fatigue Free" endurance, superior retention and imprint characteristics. In this paper, we will provide new circuits technology for FeRAM developed to implement high speed operation, low voltage operation and low power consumption. Performance of LSI embedded with FeRAM for contactless IC card is also provided to demonstrate the feasibility of the circuit technology.

The basic operation characteristics of an asymmetric turnstile which transfers each electron one by one in one direction is described. A novel single electron counter circuit consisting of the asymmetric turnstiles, a load capacitor and an inverter which counts the number of high inputs is proposed. Monte Carlo circuit simulations reveal that the gate clock time of the counter circuit should be long enough to achieve allowable minimum error rate. The counter circuit implementing asymmetric single electron turnstiles is demonstrated to be applicable to a noise reduction system, a Winner-Take-All circuit and an artificial neuron circuit.

A self-learning analog neural network LSI with non-volatile analog memory which can be updated with more than 13-bit resolution has been designed, fabricated and tasted for the first time. The non-volatile memory is attained by a new floating-gate MOSFET device that has a charge injection part and an accumulation part separated by a high resistance. We also propose a partially-serial weight-update architecture in which the plural synapse circuits use a weight-update circuit in common to reduce the circuit area. A prototype chip fabricated using a 1.3-µm double-poly CMOS process includes 50 synapse elements and its computational power is 10 MCPS. The weights can be updated at a rate of up to 40 kHz. This chip can be used to implement backpropagation networks, deterministic Boltzmann machines, and Hopfield networks with Hebbian learning.

In this paper, the error performance of block coded 8-PSK modulation systems of length 32, designed for unequal error protection (UEP) of messages transmitted over a Rayleigh fading channel, is investigated. Computer simulation are reported showing that, with transmission over a Rayleigh fading channel, a good improvement in coding gain is obtained by the use of a binary linear UEP (LUEP) code as a constituent code in the multilevel construction, compared with conventional block coded modulation (BCM) of the same length.

We have developed and operated a newly conceived multiprobe scanning force microscope (SFM) using microfabricated piezoelectric cantilevers. An array of piezoelectric microcantilevers with a piezoelectric ZnO layer on an SiO2 film makes it possible to build a multiprobe SFM system. Multiprobe SFMs are required for the application of SFM to the probe lithography and high density data storage. Each cantilever probe of multiprobe system should have a detector for sensing of its own deflection and an actuator for positioning of its tip. The piezoelectric cantilever can detect its own vibration amplitude by measuring the piezoelectric current, and it can also drive its tip by applying a voltage to the piezoelectric layer. Therefore, the piezoelectric cantilever is suitable for each cantilever of the array in the multiprobe SFM. We have verified the applicability of the piezoelectric cantilever to each lever of the array by characterizing the sensitivities of the deflection sensing and actuation. The ZnO piezoelectric cantilever with the length of 125 µm works as the z scanner with the sensitivity of 20 nm/V. We have also fabricated an experimental piezoelectric microcantilever array with ten cantilevers. We have constructed parallel operation SFM system with two cantilevers of the fabricated array and successfully obtained parallel images of 1 µm pitch grating in constant height mode.

A new magnetostrictive thin-film cantilever actuator and a new thin-film walking mechanism were developed. The actuators were made of magnetostrictive amorphous Tb-Fe and Sm-Fe thin films, deposited on the opposite sides of a polyimide film substrate. These actuators need not power supply cables because they were remotely driven by external magnetic fields. The static deflection of a 3-mm-long cantilever actuator was as large as 100 µm at 300 Oe field. Moreover the application of ac resonant frequency field of the same intensity yielded deflection of above 500 µm. The walking mechanism ran as fast as in the order of cm/s. The forward and backward running were possible depending on the frequency of applied magnetic field. Such unique characteristics suggest that magnetostrictive thin-film actuators are useful in MEMS applications.

In high-speed digital land mobile radio communication, communication quality is degraded by frequency selective fading that has intersymbol interference. It causes increase of bit error rate (BER). To decrease BER in the channel, this paper proposes a system with combined multilevel coding and adaptive equalization using interleaving. By using interleaving, the proposed system obtains time diversity effect. Furthermore the system realizes a type of decision feedback adaptive equalizer where signal after multilevel decoder is fed back. These features of the system cause decrease of BER. The proposed system is compared with a similar system with a feedback signal before multilevel decoder. The average bit error rate of the proposed system is less than 1/100 with that of the compared system at average Eb/No = 22 [dB] in a case of fading channel with one intersymbol interference.

To evaluate the coding performance of a multilevel coding scheme for Rayleigh fading channel, a virtual automatic gain control and interleaving are applied to the scheme. The automatic gain control is assumed only for the theoretical evaluation of the performance. It is noted that the bit error-rate performance of the scheme for phase shift keying does not change whether the control is assumed or not. By the effect of the virtual automatic gain control and the interleaving, a fading channel with Gaussian noise is theoretically converted into an equivalent time-invariant channel with non-Gaussian noise. The probability density function of the converted non-Gaussian noise is derived. Then, the function is applied to a formula of the bit error-rate of the scheme for non-Gaussian noise. The formula is derived for phase shift keying by modifying that for pulse amplitude modulation. The coding performance for the non-Gaussian noise channel is evaluated by the formula, and the suitable coding with ideal interleaving is searched. As a result, the coding gain of 28 dB is obtained at the bit error-rate of 10-6 by using BCH code of length 31. This result is confirmed by a simulation for the fading channel. Then, the effectiveness of the formula for finite interleaving is evaluated. Finally, the usefulness of the formula, where the noise power is doubled, is shown for a case of a differential detection.

Ferroelectic nonvolatile technology comprises the ferroelectric material technology, the process technology and the circuit technology. Bi based layered Perovskyte ferroelectric material, SrBi2Ta2O9, so called "Y 1," has superior characteristics in terms of endurance and nonvolatile properties, which is confirmed by a 256kbit ferroelectric nonvolatile memory. Critical issues regarding the ferroelectric process are reviewed. The lT/lC cell configuration which is essential for a high density memory and the reference voltage generator employed in the 256 k memory are described as is the architecture to reduce the power consumption of the memory.

An architecture for a high-density nonvolatile memory with ferroelectric capacitors is proposed and simulated. The architecture includes: (1) the operation procedure for DRAM-like memory cells with a Vcc/2 common plate, (2) commands and pin arrangement compatible with those of DRAMs. The resulting ferroelectric memory is expected to show, in addition to nonvolatility, high performance in terms of speed, active power dissipation, and read endurance. In addition, the memory can be handled in the same way as DRAMs. The proposed basic operations are confirmed by using circuit simulations, in which an equivalent circuit model for ferroelectirc capacitors is incorporated. A problem remaining with the architecture is low write endurance due to fatigue along with polarization switching. Designing the reference-voltage generator for 1T1C (one-transistor and one-capacitor) cells, while considering signal reduction along with fatigue, will be another issue for achieving high-density comparable to that of DRAMs.

A new, simple test circuit for measuring the threshold voltage distribution of flash EEPROM cell transistors is described. This circuit makes it possible to perform a reliability test for a large number of memory cell transistors with easy static operation because it reduces the measuring time drastically. In addition, this circuit can measure the highest and lowest thresh-old voltages of memory cell transistors easily. This method is suitable for performing the reliability test, such as program/erase endurance test and data retention test, for a large number of flash memory cell transistors. The usefulness of this new test circuit has been confirmed by applying it to 64 Kbit NAND-type flash memory cell array.

Extremely narrow track width of deep submicron range is examined in perpendicular magnetic recording. Head field distribution of a single-pole head analyzed by 3-dimensional computer simulation results in a sharp gradient, but relatively large cross-sectional area is required to maintain head field strength. Based on this design concept, a lateral single-pole head is described and proved to attain track width of 0.4 µm. In addition, multilevel partial response appropriate to the new multitrack recording system is proposed.

This paper reports on a new dynamic scanning force microscope (SFM), in which the piezoelectric microcantilever is utilized for the lever excitation and displacement sensing. Piezoelectric cantilevers can detect their deflection without external sensing elements and be vibrated with no oscillator outside. The cantilever integrated with the deflection detector and the oscillator changes the conventional construction of a dynamic SFM and expands its range of applicability. The microcantilever used consists of a ZnO layer sandwiched with Au electrodes deposited on a thin beam of thermally grown SiO2. The length, width and thickness of the lever are 125 µm, 50 µm and 3.5 µm, respectively. We have characterized this cantilever by measuring the charge spectrum and the frequency dependence of the admittance. From the charge spectrum the mechanical quality factor measured 300 in free vibration. Typical piezoelectric constant of the ZnO film was estimated approximately as 80% of single-crystal's value. The piezoelectric cantilever can be vibrated by applying the voltage with the frequency near the resonance to the piezoelectric layer. The excited amplitude per unit voltage at the resonance frequency was calculated as about 5 µm/V. The cantilever amplitude can be detected by measuring the current between electrodes, since the admittance depends on the quality factor. We have constructed a dynamic SFM without external oscillator and detector, and successfully obtained the surface images of a sol-gel derived PZT film in the cyclic contact operation mode. The longitudinal resolution of the SFM system was 0.3 nm at a 125 Hz bandwidth.

This paper proposes a new approach to the management of large-scale communication networks. To manage large-scale communication networks effectively, it is essential to get a bird's-eye view of them when they are in their normal conditions. When an indication of faulty state is detected, the focus of the management is narrowed down to the faulty network elements until the appropriate granularity is reached. This management scheme is called multilevel network management in this paper, and it first explains the significance of this scheme for large-scale communication networks and presents some ideas on implementing this management scheme. It then proposes that system identification be used in multilevel network management. The system identification is used to measure transmission delays between two arbitrarily selected nodes in the networks, and multilevel network management is achieved by selecting those two nodes appropriately in accordance with the levels to be managed. Finally, it is demonstrated by computation simulation results that the proposed method is suitable for multilevel network management.

This paper proposes a new signaling technique which employs multilevel block codes in conjunction with phase/frequency modulation. The proposed scheme exhibits an increased minimum squared Euclidean distances (MSEDs) and outperforms other conventional schemes in terms of asymptotic coding gain and decoding complexity. The proposed scheme is also considered for non-constant amplitudes, which turned out to show even better performances at small modulation indices in some cases. Examples are given to demonstrate how to optimize the signal set for a given block code to maximize the coding gain.

A low-voltage operation and highly-reliable nonvoltatile semiconductor memory with a large capacity has been manufactured using 0.8-µm CMOS technology. This 3-volt, 1-Mbit, full-featured MONOS EEPROM has a chip size of 51.3 mm2 and a memory cell size of 23.1µm2. An asymmetric programming voltage method fully exploits the abilities of the MONOS device and provides 10-year data retention after 106 erase/write cycles. Because of its wide-margin circuit design, this EEPROM can also be operated at 5 volts. High-speed read out is provided by using the polycide word line and the differential sense amplifier with a MONOS dummy memory. New functions such as data protection with software and programming-end indication with a toggle bit are added, and chips are TSOP packaged for use in many kinds of portable equipment.