The tiled-display system has been used as a Computer Supported Cooperative Work (CSCW) environment, in which multiple local (and/or remote) participants cooperate using some shared applications whose outputs are displayed on a large-scale and high-resolution tiled-display, which is controlled by a cluster of PC's, one PC per display. In order to make the collaboration effective, each remote participant should be aware of all CSCW activities on the titled display system in real-time. This paper presents a capturing and delivering mechanism of all activities on titled-display system to remote participants in real-time. In the proposed mechanism, the screen images of all PC's are periodically captured and delivered to the Merging Server that maintains separate buffers to store the captured images from the PCs. The mechanism selects one tile image from each buffer, merges the images to make a screen shot of the whole tiled-display, clips a Region of Interest (ROI), compresses and streams it to remote participants in real-time. A technical challenge in the proposed mechanism is how to select a set of tile images, one from each buffer, for merging so that the tile images displayed at the same time on the tiled-display can be properly merged together. This paper presents three selection algorithms; a sequential selection algorithm, a capturing time based algorithm, and a capturing time and visual consistency based algorithm. It also proposes a mechanism of providing several virtual cameras on tiled-display system to remote participants by concurrently clipping several different ROI's from the same merged tiled-display images, and delivering them after compressing with video encoders requested by the remote participants. By interactively changing and resizing his/her own ROI, a remote participant can check the activities on the tiled-display effectively. Experiments on a 32 tiled-display system show that the proposed merging algorithm can build a tiled-display image stream synchronously, and the ROI-based clipping and delivering mechanism can provide individual views on the tiled-display system to multiple remote participants in real-time.

A HfO2 as the charge-storage layer with the physical thickness thinner than 4 nm in silicon-oxide-high-k oxide-oxide-silicon (SOHOS) flash memory was investigated. Compared to the conventional silicon-oxide-nitride-oxide-silicon (SONOS) flash memory, the SOHOS shows the slow operational speed and exhibits the poorer retention characteristics. These are attributed to the thin physical thickness below 4 nm and the crystallization of the HfO2 to contribute the lateral migration of the trapped charge in the trapping layer during high temperature annealing process.

The multilevel dual-channel (MLDC) not-AND (NAND) flash memories cell structures with asymmetrically-doped channel regions between the source and the drain were proposed to enhance read and program verifying speeds. The channel structure of the MLDC flash memories consisted of two different doping channel regions. The technical computer aided design simulation results showed that the designed MLDC NAND flash cell with asymmetrically-doped channel regions provided the high-speed multilevel reading with a wider current sensing margin and the high-speed program verifying due to the sensing of the discrete current levels. The proposed unique MLDC NAND flash memory device can be used to increase read and program verifying speed.

File systems make use of the buffer cache to enhance their performance. Traditionally, part of DRAM, which is volatile memory, is used as the buffer cache. In this paper, we consider the use of of Non-Volatile RAM (NVRAM) as a write cache for metadata of the file system in embedded systems. NVRAM is a state-of-the-art memory that provides characteristics of both non-volatility and random byte addressability. By employing NVRAM as a write cache for dirty metadata, we retain the same integrity of a file system that always synchronously writes its metadata to storage, while at the same time improving file system performance to the level of a file system that always writes asynchronously. To show quantitative results, we developed an embedded board with NVRAM and modify the VFAT file system provided in Linux 2.6.11 to accommodate the NVRAM write cache. We performed a wide range of experiments on this platform for various synthetic and realistic workloads. The results show that substantial reductions in execution time are possible from an application viewpoint. Another consequence of the write cache is its benefits at the FTL layer, leading to improved wear leveling of Flash memory and increased energy savings, which are important measures in embedded systems. From the real numbers obtained through our experiments, we show that wear leveling is improved considerably and also quantify the improvements in terms of energy.

MOS capacitors with Si-implanted thermal oxide and CVD deposited oxide of 30 nm thickness were fabricated for applications of non-volatile memory and electroluminescence devices. Current-voltage (I-V) and I-V hysteresis characteristics were measured, and the hysteresis window (HW) and the integrated charge of HW (ICHW) extracted from the hysteresis data were discussed. The HW characteristics of high Si dose samples showed the asymmetrical double-peaks curves with the hump in both tails. The ICHW almost converged after the 4th cycle and had the voltage sweep speed dependence. All +ICHW and -ICHW characteristics were closely related to the static (+I)-(+VG) and (-I)-(-VG) curves, respectively. For the high Si dose samples, the clear hump currents in the static I-VG characteristics contribute to lower the rising voltage and to steepen the ICHW increase, which correspond to the large stored charge in the oxide.

Recently, various types of 3-D nonvolatile memory (NVM) devices have been researched to improve the integration density [1]-[3]. The NVM device of pillar structure can be considered as one of the candidates [4],[5]. When this is applied to a NAND flash memory array, bottom end of the device channel is connected to the bulk silicon. In this case, the current in vertical direction varies depending on the thickness of silicon channel. When the channel is thick, the difference of saturation current levels between on/off states of individual device is more obvious. On the other hand, when the channel is thin, the on/off current increases simultaneously whereas the saturation currents do not differ very much. The reason is that the channel potential barrier seen by drain electrons is lowered by read voltage on the opposite sidewall control gate. This phenomenon that can occur in 3-D structure devices due to proximity can be called gate-induced barrier lowering (GIBL). In this work, the dependence of GIBL on silicon channel thickness is investigated, which will be the criteria in the implementation of reliable ultra-small NVM devices.

Halftoning is an important process to convert a gray scale image into a binary image with black and white pixels. The Direct Binary Search (DBS) is one of the well-known halftoning methods that can generate high quality binary images for middle tone of original gray scale images. However, binary images generated by the DBS have clippings, that is, have no tone in highlights and shadows of original gray scale images. The first contribution of this paper is to show the reason why the DBS generates binary images with clippings, to clarify the range of tone in original images that may have clipping, and to present a clipping-free DBS-based halftoning algorithm. The key idea is to apply the ordered dither using a threshold array generated by DBS-based method, to highlights and shadows, and then use the DBS. The second contribution is to extend the DBS to generate L-level multitone images with each pixel taking one of the intensity levels , , ..., . However, clippings appear in highlights, middle tone, and shadows of generated L-level multitone images. The third contribution of this paper is to modify the multitone version of the DBS to generate a clipping-free L-level multitone images. The resulting multitone images are so good that they reproduce the tones and the details of the original gray scale images very well.

In this paper, we propose and analyze a multi-level acknowledgement scheme for hybrid ARQ (H-ARQ) systems, which modifies the general ACK/NAK signals to represent multilevel information. For instance, the other signals except the ACK/NAK signals may be used for scheduling of retransmission in the H-ARQ scheme, which results in increasing the resolution of the uplink channel estimation signals. Simulation results demonstrate that when the retransmission interval is set to the optimal length, the proposed H-ARQ scheme shows a 0.5-2 dB gain with properly selected parameters.

We fabricated the floating gate for silicon-on-insulator nonvolatile memory devices with In2O3 nano-particles embedded in polyimide insulator. Self-assembled In2O3 nano-particles were created by chemical reaction between the biphenyl dianhydride-p-phenylenediamine polymer precursor and indium films. The particles size and density of In2O3 nano-particles were 7 nm and 61011 cm-2, respectively. The current-voltage and retention time of fabricated device were characterized by using semiconductor parameter analyzer. A significant threshold voltage shift of fabricated nano-floating gate memory devices obtained, because of the charging effects of In2O3 nano-particles. And a memory window measured about 1 V at initial status.

The reduction of a structural pattern at specific gray levels or at the special condition of image data has mainly been discussed in digital halftone methods. This problem is more severe in some flat panel displays because their black levels typically are brighter than other displays blocks. The authors proposed an advanced confined error diffusion (ACED) algorithm which was a well-organized halftone algorithm for flat panel devices. In this paper, we extend the ACED algorithm to the multi-level systems, which are capable of displaying more than 2 levels. Our extension has two merits for the hardware implementation. First, it can be processed in real time using the look-up table based method. The second one is the flexibility of selecting the used gray level. This paper discusses the performance of the proposed algorithms with experimental results for natural test images.

A 4-Gb AG-AND flash memory was fabricated by using a 90-nm CMOS technology. To reduce cell size, an inversion-layer-bit-line technology was developed, enabling the elimination of both shallow trench isolations and diffusion layers from the memory cells. The inversion-layer-bit-line technology combined with a multilevel cell technique achieved a bit area 2F2 of 0.0162 µm2, resulting in a chip size of 126 mm2. Both an address and temperature compensation techniques control the resistance of the inversion-layer local bit line. Source-side hot-electron injection programming with self-boosted charge, accumulated in inversion-layer bit lines under assist gates, reduces the dispersal of programming characteristics and also reduces the time overhead of pre-charging the bit lines. This self-boosted charge-injection scheme achieves a programming throughput of 10 MB/s.

The electric fields inside and outside a car must be carefully determined when designing a wireless communication system to be employed in the car. This paper introduces an effective simulation method and a precise measurement method of electric field distributions in a cabin of a simplified scale car model. A 1/3 car model is employed for ease of measurement. The scaled frequency of 2859 MHz, 3 times 953 MHz, is employed. The use of a moment method simulator utilizing the multilevel fast multipole method allows calculations to be performed on a personal computer. In order to judge the accuracy of simulation results, convergence of simulation output in accordance with segment size (triangle edge length) changes is ensured. Simulation loads in the case of metallic body only and a metallic body with window glass are also shown. In the measurements, an optical electric field probe is employed so as to minimize the disturbances that would otherwise be caused by metallic feed cable; precise measurement results are obtained. Comparisons of measured and simulated results demonstrate very good agreement which confirms the accuracy of the calculated results. 3-dimensional electric field distributions in the car model are shown and 3-dimensional standing wave shapes are clarified. Moreover, calculated and measured radiation patterns of the car model are shown so the total electric field distributions around a car are clarified.

In order to support driving safety, TPMS (Tire Pressure Monitoring System) has been introduced in U.S.A. and Europe. In Japan, the AIRwatch system has been developed and commercialized. Some studies were made to clarify the electric field environment of this system. However, no detailed calculation of the electric field between the transmitter in the tire and the receiving antenna has been published. This paper clarifies the electric field environment of the Japanese system through electromagnetic simulations by a high performance MoM simulator that utilizes the MLFMM scheme. First of all, electric wave emissions from an antenna mounted in a tire are shown to be larger than that of the same antenna in free space. The tire rubber effects are also investigated. Next, electric field distributions on the windshield holding the receiving antenna are calculated. By comparing calculated electric field levels with those in the free space condition, car body interruptions are clarified. Because car body interruptions are not so severe, it is shown that the free space electric field levels can be used as rough design parameters. Moreover, electric field changes due to tire rotation are also clarified. Calculation accuracy is confirmed by the good agreement with measured data collected from a 1/5 scale car model. To permit estimations to be made in actual situations, the effects of the ground are also investigated. This simulation study introduces a lot of important data useful in TPMS system design.

A single-electron turnstile and electrometer circuit was fabricated on a silicon-on-insulator substrate. The turnstile, which is operated by opening and closing two metal-oxide-semiconductor field-effect transistors (MOSFETs) alternately, allows current quantization at 20 K due to single-electron transfer. Another MOSFET is placed at the drain side of the turnstile to form an electron storage island. Therefore, one-by-one electron entrance into the storage island from the turnstile can be detected as an abrupt change in the current of the electrometer, which is placed near the storage island and electrically coupled to it. The correspondence between the quantized current and the single-electron counting was confirmed.

Existing vision substitute systems have insufficient spatial resolution to provide environmental information. To present detailed spatial information, we propose two stimulation methods to enhance transfer information using a 2-D tactile stimulator array. First, stimulators are divided into several groups. Since each stimulator group is activated alternately, the interval of stimulations can be shortened to less than the two-point discrimination threshold. In the case that stimulators are divided into two and four groups, the number of stimulators increases to twice and four times, respectively, that in the case of the two-point discrimination threshold. Further, a user selects the measurement range and the system presents targets within the range. The user acquires spatial information of the entire measurement area by changing the measurement range. This method can accurately present a range of targets. We examine and confirm these methods experimentally.

A novel PND (PMOS-NMOS-Depletion MOS) technology for a single poly gate non-volatile memory cell design has been reported for the first time. This technology features memory cell design with a differential cell architecture which enables to provide the higher performance for the key specifications such as programming time, erasing time, and endurance characteristics. This memory cell consists of 3-Transistors, PMOS, NMOS, and Depletion MOS transistors (hereafter PND). The DMOS in this cell is used for the tunneling device in the erasing operation, while the NMOS and the PMOS are used for the tunneling device and the coupling capacitor in the programming operation, respectively. The proposed PND design can allow lower applied voltage of the erase-gate (EG) and control-gate (CG) in the erasing and the programming operations so that the endurance characteristics can be improved because the DMOS suppresses the potential of floating-gate (FG) and hence the effective potential difference between the EG and the FG can be increased in the erasing operation. Based on the measured data, it can be expected that the erasing speed of the PND cell can be 125-fold faster than that of our previously reported work (PN type). Therefore, high performance and high reliability CMOS non-volatile memory without any additional process can be realized using this proposed PND technology.

We developed a selective-capacitance constant-charge-injection programming (CCIP) scheme to achieve high programming throughput in multilevel assist-gate (AG)-AND flash memories. In the conventional CCIP scheme, only one type of capacitance for storing programming charge was used for all levels of multilevel cells. The proposed scheme utilized multiple types of capacitance to minimize the programming time of all levels by using optimized capacitance values for each Vth level. In 4-Gbit AG-AND flash memories, a local bit line capacitance is utilized for mid-level programming, and the sum of local and global bit line capacitance is utilized for top-level programming. In addition, we developed a verify-less programming scheme which reduces top-level programming time because it is not necessary to verify the top-level of multilevel cells in AND flash memory architecture. A programming throughput of 10 MB/s is achieved using the proposed schemes. This is 1.6 times faster than the throughput with conventional CCIP.

This paper presents a simple and effective method to further reduce the search points in multilevel successive elimination algorithm (MSEA). Because the calculated sea values of those best matching search points are much smaller than the current minimum SAD, we can simply increase the calculated sea values to increase the elimination ratio without much affecting the coding quality. Compared with the original MSEA algorithm, the proposed strict MSEA algorithm (SMSEA) can provide average 6.52 times speedup. Compared with other lossy fast ME algorithms such as TSS and DS, the proposed SMSEA can maintain more stable image quality. In practice, the proposed technique can also be used in the fine granularity SEA (FGSEA) algorithm and the calculation process is almost the same.

The performance of a new APSK receiver is analyzed using numerical simulation. The proposed receiver eliminates the penalty caused by SPM-induced phase-shift of optical pulses by employing three sub-modules and an amplitude-pattern controlled switch for each DPSK tributary. The interplay between SPM, IXPM, and XPM determines the performance of the proposed receiver for single-channel and WDM transmission.

A novel ratio-oriented definition based on 2T2R (Two transistors & two phase change resistors) phase change memory (PCM) cell structure is proposed to gain a high density by multilevel storage. In this novel solution, no reference is needed and good robustness remains still as conventional 2T2R, which is crucial when feature size scales to nanometer technology node. A behavioral SPICE model together with a preliminary simulation proves the idea to be feasible, and further optimization has been carried out. In addition, based on the ratio-oriented definition, a simpler and faster Error Control Coding (ECC) can be realized with n-Error-detection feasible.