The write operations on emerging Non-Volatile Memory (NVM), such as NAND Flash and Phase Change Memory (PCM), usually incur high access latency, and are required to be optimized. In this paper, we propose Asymmetric Read-Write (ARW) policies to minimize the write traffic sent to NVM. ARW policies exploit the asymmetry costs of read and write operations, and make adjustments on the insertion policy and hit-promotion policy of the replacement algorithm. ARW can reduce the write traffic to NVM by preventing dirty data blocks from frequent evictions. We evaluate ARW policies on systems with PCM as main memory and NAND Flash as disk. Simulation results on an 8-core multicore show that ARW adopted on the last-level cache (LLC) can reduce write traffic by more than 15% on average compared to LRU baseline. When used on both LLC and DRAM cache, ARW policies achieve an impressive reduction of 40% in write traffic without system performance degradation. When employed on the on-disk buffer of the Solid State Drive (SSD), ARW demonstrates significant reductions in both write traffic and overall access latency. Moreover, ARW policies are lightweight, easy to implement, and incur negligible storage and runtime overhead.

Non-volatile memories are paid attention to as a promising alternative to memory design. Data stored in them still may be destructed due to crosstalk and radiation. We can restore the data by using error-correcting codes which require extra bits to correct bit errors. Further, non-volatile memories consume ten to hundred times more energy than normal memories in bit-writing. When we configure them using error-correcting codes, it is quite necessary to reduce writing bits. In this paper, we propose a method to generate a bit-write-reducing code with error-correcting ability. We first pick up an error-correcting code which can correct t-bit errors. We cluster its codeswords and generate a cluster graph satisfying the S-bit flip conditions. We assign a data to be written to each cluster. In other words, we generate one-to-many mapping from each data to the codewords in the cluster. We prove that, if the cluster graph is a complete graph, every data in a memory cell can be re-written into another data by flipping at most S bits keeping error-correcting ability to t bits. We further propose an efficient method to cluster error-correcting codewords. Experimental results show that the bit-write-reducing and error-correcting codes generated by our proposed method efficiently reduce energy consumption. This paper proposes the world-first theoretically near-optimal bit-write-reducing code with error-correcting ability based on the efficient coding theories.

In this letter, we propose a garbage collection technique for non-volatile memory systems, called Migration Cost Sensitive Garbage Collection (MCSGC). Considering the migration overhead from selecting victim blocks, MCSGC increases the lifetime of memory systems and improves response time in garbage collection. Additionally, the proposed algorithm also improves the efficiency of garbage collection by separating cold data from hot data in valid pages. In the experimental evaluation, we show that MCSGC yields up to a 82% improvement in lifetime prolongation, compared with existing garbage collection, and it also reduces erase and migration operations by up to 30% and 29%, respectively.

This paper presents a scheme that digitally cancels the unwanted phase components generated by the transmitter's laser and the receiver's local oscillator laser; such components place a substantial limit on the performance of coherent transceivers monolithically integrated with lasers in a photonic integrated circuit (PIC). Our cancellation proposal adopts the orthogonal polarization approach to provide a reference that is uncorrelated with the data signal. We elaborate on the principle of our proposal and its digital signal processing (DSP) algorithm. Experiments on a VCSEL with a linewidth of approximately 300MHz verify that our proposal can overcome the inherent phase noise limitations indicated by simulations and experiments. Our cancellation algorithm in conjunction with CMA-based polarization control is demonstrated and evaluated to confirm the feasibility of our proposal. The achievement of greatly relaxed laser linewidth will offer a significant benefit in offsetting the technical and cost requirements of coherent transceiver PICs with lasers. Therefore, our cancellation proposal is an enabling technology for the successful deployment of future coherent-based passive optical network (PON) systems.

Diabetes mellitus is a group of metabolic diseases that cause high blood sugar due to functional problems with the pancreas or metabolism. Diabetic patients have few subjective symptoms and may experience decreased sensation without being aware of it. The commonly performed tests for sensory disorders are qualitative in nature. The authors pay attention to the decline of the sensitivity of tactile sensations, and develop a non-invasive method to detect the level of tactile sensation using a novel micro-vibration actuator that employs shape-memory alloy wires. Previously, we performed a pilot study that applied the device to 15 diabetic patients and confirmed a significant reduction in the tactile sensation in diabetic patients when compared to healthy subjects. In this study, we focus on the asymptomatic development of decreased sensation associated with diabetes mellitus. The objectives are to examine diabetic patients who are unaware of abnormal or decreased sensation using the quantitative tactile sensation measurement device and to determine whether tactile sensation is decreased in patients compared to healthy controls. The finger method is used to measure the Tactile Sensation Threshold (TST) score of the index and middle fingers using the new device and the following three procedures: TST-1, TST-4, and TST-8. TST scores ranged from 1 to 30 were compared between the two groups. The TST scores were significantly higher for the diabetic patients (P<0.05). The TST scores for the left fingers of diabetic patients and healthy controls were 5.9±6.2 and 2.7±2.9 for TST-1, 15.3±7.0 and 8.7±6.4 for TST-4, and 19.3±7.8 and 12.7±9.1 for TST-8. Our data suggest that the use of the new quantitative tactile sensation measurement device enables the detection of decreased tactile sensation in diabetic patients who are unaware of abnormal or decreased sensation compared to controls.

We have developed software that uses the R statistics software environment to automatically generate tactile graphs — i.e. graphs that can be read by blind people using their sense of touch. We released this software as a Web application to make it available to anyone, from anywhere. This Web application can automatically generate images for tactile graphs from numerical data in a CSV file. It is currently able to generate four types of graph — scatter plots, line graphs, bar charts and pie charts. This paper describes the Web application's functions, operating procedures and the results of evaluation experiments.

Data stored in non-volatile memories may be destructed due to crosstalk and radiation but we can restore their data by using error-correcting codes. However, non-volatile memories consume a large amount of energy in writing. How to reduce maximum writing bits even using error-correcting codes is one of the challenges in non-volatile memory design. In this paper, we first propose Doughnut code which is based on state encoding limiting maximum and minimum Hamming distances. After that, we propose a code expansion method, which improves maximum and minimum Hamming distances. When we apply our code expansion method to Doughnut code, we can obtain a code which reduces maximum-flipped bits and has error-correcting ability equal to Hamming code. Experimental results show that the proposed code efficiently reduces the number of maximum-writing bits.

Non-volatile memory has many advantages such as high density and low leakage power but it consumes larger writing energy than SRAM. It is quite necessary to reduce writing energy in non-volatile memory design. In this paper, we propose write-reduction codes based on error correcting codes and reduce writing energy in non-volatile memory by decreasing the number of writing bits. When a data is written into a memory cell, we do not write it directly but encode it into a codeword. In our write-reduction codes, every data corresponds to an information vector in an error-correcting code and an information vector corresponds not to a single codeword but a set of write-reduction codewords. Given a writing data and current memory bits, we can deterministically select a particular write-reduction codeword corresponding to the data to be written, where the maximum number of flipped bits are theoretically minimized. Then the number of writing bits into memory cells will also be minimized. Experimental results demonstrate that we have achieved writing-bits reduction by an average of 51% and energy reduction by an average of 33% compared to non-encoded memory.

We present an electrostatic tactile display for stimulus localization. The 240-Hz electrostatic force was generated by the beat phenomenon in a region where excited X electrodes cross excited Y electrodes, which presents localized tactile sensation out of the entire surface. A 10.4-in. visual-tactile integrated display was successfully demonstrated.

A ferroelectric-based (FE-based) non-volatile logic is proposed for low-power LSI. Standby currents in a logic circuit can be cut off by using FE-based non-volatile flip-flops (NVFFs), and the standby power can be reduced to zero. The FE capacitor is accessed only when the power turns on/off, performance of the NVFF is almost as same as that of the conventional flip-flop (FF) in a logic operation. The use of complementarily stored data in coupled FE capacitors makes it possible to realize wide read voltage margin, which guarantees 10 years retention at 85 degree Celsius under less than 1.5V operation. The low supply voltage and electro-static discharge (ESD) detection technique prevents data destruction caused by illegal access for the FE capacitor during standby state. Applying the proposed circuitry in CPU, the write and read operation for all FE capacitors in 1.6k-bit NVFFs are performed within 7µs and 3µs with access energy of 23.1nJ and 8.1nJ, respectively, using 130nm CMOS with Pb(Zr,Ti)O3(PZT) thin films.

Braille fonts allow us to easily make braille labels on capsule paper. For legibility, fonts should be printed at optimum sizes. To find the optimum sizes for Japanese braille fonts, we conducted an experiment in which a Japanese braille font was printed at various sizes on capsule paper and read and rated by young braille users. The results show that braille printed at 17 and 18 point sizes were read faster and evaluated higher than those printed at smaller or bigger sizes.

Non-Volatile Memories (NVMs) are considered as promising memory technologies for Last-Level Cache (LLC) due to their low leakage and high density. However, NVMs have some drawbacks such as high dynamic energy in modifying NVM cells, long latency for write operation, and limited write endurance. A number of approaches have been proposed to overcome these drawbacks. But very little attention is paid to consider the cache coherency issue. In this letter, we suggest a new cache coherence protocol to reduce the write operations of the LLC. In our protocol, the block data of the LLC is updated only if the cache block is written-back from a private cache, which leads to avoiding useless write operations in the LLC. The simulation results show that our protocol provides 27.1% energy savings and 26.3% lifetime improvements in STT-RAM at maximum.

This paper describes experiments on passive Multiple-Input Multiple-Output (MIMO) transmission with load modulation. PIN diodes are used as the variable impedance element at the tag side to realize multi-level modulation. The results indicate that the transmission rate of passive MIMO is up to 2 times higher than that of Single-Input Single-Output (SISO) with the same transmission power when the distance between the reader and the tag is 0.5m. Also, when the distance is 1m, MIMO offers up to 1.7 times higher transmission rate than SISO. These results indicate that passive MIMO offers high-speed data transmission even when the distance is doubled.

The paper presents ultra-high-capacity transmission technologies based on multi-core space-division-multiplexing. In order to realize high-capacity multi-core fiber (MCF) transmission, investigation of low crosstalk fiber and connection technology is important, and high-density signal generation using multilevel modulation and crosstalk management are also key technologies. 1Pb/s multi-core fiber transmission experiment using space-division-multiplexing is also described.

The present study aims to investigate the effect of voluntary movements on human temporal perception in multisensory integration. We therefore performed temporal order judgment (TOJ) tasks in audio-tactile integration under three conditions: no movement, involuntary movement, and voluntary movement. It is known that the point of subjective simultaneity (PSS) under the no movement condition, that is, normal TOJ tasks, appears when a tactile stimulus is presented before an auditory stimulus. Our experiment showed that involuntary and voluntary movements shift the PSS to a value that reduces the interval between the presentations of auditory and tactile stimuli. Here, the shift of the PSS under the voluntary movement condition was greater than that under the involuntary movement condition. Remarkably, the PSS under the voluntary movement condition appears when an auditory stimulus slightly precedes a tactile stimulus. In addition, a just noticeable difference (JND) under the voluntary movement condition was smaller than those under the other two conditions. These results reveal that voluntary movements alternate the temporal integration of audio-tactile stimuli. In particular, our results suggest that voluntary movements reverse the temporal perception order of auditory and tactile stimuli and improve the temporal resolution of temporal perception. We discuss the functional mechanism of shifting the PSS under the no movement condition with voluntary movements in audio-tactile integration.

In this paper, we propose an optimum access method for a phase change memory (PCM) with NAND strings. A PCM with a block erase interface is proposed. The method, which has a SET block erase operation and fast RESET programming, is proposed since the SET operation causes a slow access time for conventional PCM;. From the results of measurement, the SET-ERASE operation is successfully completed while the RESET-ERASE operation is incomplete owing to serial connection. As a result, the block erase interface with the SET-ERASE and RESET program method realizes a 7.7 times faster write speed compared than a conventional RAM interface owing to the long SET time. We also give pass-transistor design guidelines for PCM with NAND strings. In addition, the write-capability and write-disturb problems are investigated. The ERASE operation for the proposed device structure can be realized with the same current as that for the SET operation of a single cell. For the pass transistor, about 4.4 times larger on-current is needed to carry out the RESET operation and to avoid the write-disturb problem than the minimum RESET current of a single cell. In this paper, the SET programming method is also verified for a conventional RAM interface. The experimental results show that the write-capability and write-disturb problems are negligible.

Traditionally, in computer systems, file I/O has been a big performance bottleneck for I/O intensive applications. The recent advent of non-volatile byte-addressable memory (NVM) technologies such as STT-MRAM and PCM, provides a chance to store persistent data with a high performance close to DRAM's. However, as the location of the persistent storage device gets closer to the CPU, the system software layers overheads for accessing the data such as file system layer including virtual file system layer and device driver are no longer negligible. In this paper, we propose a light-weight user-level persistent storage, called UStore, which is physically allocated on the NVM and is mapped directly into the virtual address space of an application. UStore makes it possible for the application to fast access the persistent data without the system software overheads and extra data copy between the user space and kernel space. We show how UStore is easily applied to existing applications with little elaboration and evaluate its performance enhancement through several benchmark tests.

Nonvolatile flip-flop enables leakage power reduction in logic circuits and quick return from standby mode. However, it has limited write endurance, and its power consumption for writing is larger than that of conventional D flip-flop (DFF). For this reason, it is important to reduce the number of write operations. The write operations can be reduced by stopping the clock signal to synchronous flip-flops because write operations are executed only when the clock is applied to the flip-flops. In such clock gating, a method using Exclusive OR (XOR) of the current value and the new value as the control signal is well known. The XOR based method is effective, but there are several cases where the write operations can be reduced even if the current value and the new value are different. The paper proposes a method to detect such unnecessary write operations based on state transition analysis, and proposes a write control method to save power consumption of nonvolatile flip-flops. In the method, redundant bits are detected to reduce the number of write operations. If the next state and the outputs do not depend on some current bit, the bit is redundant and not necessary to write. The method is based on Binary Decision Diagram (BDD) calculation. We construct write control circuits to stop the clock signal by converting BDDs representing a set of states where write operations are unnecessary. Proposed method can be combined with the XOR based method and reduce the total write operations. We apply combined method to some benchmark circuits and estimate the power consumption with Synopsys NanoSim. On average, 15.0% power consumption can be reduced compared with only the XOR based method.

A modified modeling of residue effect on nano-electro-mechanical nonvolatile memory (NEMory) is presented for considering wet etching process. The effect of a residue under the cantilever is investigated for the optimization. The feasibility of the proposed model is investigated by finite element analysis simulations.

In summary, we successfully fabricated the nonvolatile hybrid polymer 4F2 memory-cell. It was based on bistable state, which was observed in PS layer that is containing a Ni nanocrystals capped with NiO tunneling barrier sandwiched by Al electrodes. The current conduction mechanism for polymer memory-cell was demonstrated by fitting the I-V curves. The electrons were charged and discharged on Ni nanocrystals by tunneling through the NiO tunneling barrier. In addition, the memory-cell showed a good and reproducible nonvolatile memory-cell characteristic. Its memory margin is about 1.410. The retention-time is more than 105 seconds and the endurance cycles of program-and-erase is more than 250 cycles. Furthermore, Thefore, polymer memory-cell would be good candidates for nonvolatile 4F2 cross-bar memory-cell.