Compiling documents in extensible markup language (XML) increasingly requires access to data services which provide both rapid response and the precise use of search engines. Efficient data service should be based on a skillful representation that can support low complexity and high precision search capabilities. In this paper, a novel complete path representation (CPR) associated with a modified inverted index is presented to provide efficient XML data services, where queries can be versatile in terms of predicates. CPR can completely preserve hierarchical information, and the new index is used to save semantic information. The CPR approach can provide template-based indexing for fast data searches. An experiment is also conducted for the evaluation of the CPR approach.

This letter presents a framework, including two constructions, for yielding several types of sequences with optimal autocorrelation properties. Only by simply choosing proper coefficients in constructions and optimal known sequences, two constructions transform the chosen sequences into optimally required ones with two or four times periods as long as the original sequences', respectively. These two constructions result in binary and quaternary sequences with optimal autocorrelation values (OAVs), perfect QPSK+ sequences, and multilevel perfect sequences, depending on choices of the known sequences employed. In addition, Construction 2 is a generalization of Construction B in [5] so that the number of distinct sequences from the former is larger than the one from the latter.

New concept of CMOS nonvolatile memory is presented with demonstration of cell implementations. The memory cell, which is a comparator basically, makes use of comparator offset for storage quantity and the FN stress phenomena for cell programming. We also propose the stress-packet operation which is the relevant programming method to finely control the offset of the memory cell. The memory cell is multiple-time programmable while it is implemented in a standard CMOS process. We fabricated the memory cell arrays of the latch comparator and demonstrated that it is rewritten several times. We also investigated the reliability of cell data retention by monitoring programmed offsets for several months.

The fringe field effects of nano-electromechanical (NEM) nonvolatile memory cells have been investigated analytically for the accurate evaluation of NEM memory cells. As the beam width is scaled down, fringe field effect becomes more severe. It has been observed that pull-in, release and hysteresis voltage decrease more than our prediction. Also, the fringe field on cell characteristics has been discussed.

In this paper, we propose a new low power nonvolatile counter unit based on Magnetic Tunnel Junction (MTJ) with fine-grained power gating. The proposed counter unit consists of only a single latch with two MTJs. We verify the basic operation and estimate the power consumption of the proposed counter unit. The operating power consumption of the proposed nonvolatile counter unit is smaller than the conventional one below 140 kHz. The power of the proposed unit is 74.6% smaller than the conventional one at low frequency.

In this paper, a 60 nm-thick ferroelectric film of poly(vinylidene fluoride–trifluoroethylene) on a flexible substrate of aluminum foil was fabricated and characterized. Compared to pristine silicon wafer, Al-foil has very large root-mean-square (RMS) roughness, thus presenting challenges for the fabrication of flat and uniform electronic devices on such a rough substrate. In particular, RMS roughness affects the leakage current of dielectrics, the uniformity of devices, and the switching time in ferroelectrics. To avoid these kinds of problems, a new thin film fabrication method adopting a detach-and-transfer technique has been developed. Here, 'detach' means that the ferroelectric film is detached from a flat substrate (sacrificial substrate), and 'transfer' refers to the process of the detached film being moved onto the rough substrate (main substrate). To characterize the dielectric property of the transferred film, polarization and voltage relationships were measured, and the results showed that a hysteresis loop could be obtained with low leakage current.

Error analysis of the multilevel fast multipole algorithm is studied for electromagnetic scattering problems. We propose novel error prediction and control methods and verify that the computational error for scattering problems with over one million unknowns can be precisely controlled under desired digits of accuracy. Optimum selection of truncation numbers to minimize computational error also will be discussed.

In this study, we demonstrate an acceleration of flexible generalized minimal residual algorithm (FGMRES) implemented with the method of moments and the fast multipole method (FMM), based on a combined tangential formulation. For the implementation of the FGMRES incorporated with the FMM concept, we propose a new definition of the truncation number for the FMM operator within the inner solver. The proposed truncation number provides an optimal variable preconditioner by controlling the accuracy and computational cost of the inner iteration. Moreover, to further accelerate the convergence, we introduce the concept of a multistage preconditioner. Numerical experiments reveal that our new version of FGMRES, based on the proposed truncation number for the inner solver and the multistage preconditioner, achieves outstanding acceleration of the convergence for large-scale and practical electromagnetic scattering and radiation problems with several levels of geometrical complexity.

This paper presents a content-addressable memory (CAM) using a phase-change device. A hierarchical match-line structure and a one-hot-spot block code are indispensable to suppress the resistance ratio of the phase-change device and the area overhead of match detectors. As a result, an 8-nsec 72-bit-parallel-search CAM is implemented using a phase-change-device/MOS-hybrid circuitry, where high and low resistances are higher than 2.3 MΩ and lower than 97 kΩ, respectively, while maintaining one-day retention.

In summary, we successfully developed the polymer nonvolatile 4F2 memory-cell. It was based on nonvolatile memory characteristics such as memory margin and retention time, which was observed in memory-cell embedded with Ag nanocrystals in PVK layer. The nonvolatile memory characteristics depend on the shape, distribution and isolation of Ag nanocrystals. Accordingly, the thickness of Ag film has an important role in optimizing the Ag nanocrystals. Therefore, the polymer nonvolatile memory-cell is fabricated by appropriate thickness of film and need an improvement of interface between Ag nanocrystals and PVK for sufficient nonvolatile memory characteristics.

We report a fast single element nonvolatile memory that employs amorphous to crystalline phase change. Temperature change is induced within a single electronic element in confined geometry transistors to cause the phase change. This novel phase change memory (PCM) operates without the need for charge transport through insulator films for charge storage in a floating gate. GeSbTe (GST) was employed to the phase change material undergoing transition below 200. The phase change, causing conductivity and permittivity change of the film, results in the threshold voltage shift observed in transistors and capacitors.

Due to the aggressive scaling of non-volatile memories, “charge-trap memories” such as MONOS-type memories become one of the most important targets. One of the merits of such MONOS-type memories is that they can trap charges inside atomic-scale defect sites in SiN layers. At the same time, however, charge traps with atomistic scale tend to induce additional large structural changes. Hydrogen has attracted a great attention as an important heteroatom in MONOS-type memories. We theoretically investigate the basic characteristics of hydrogen-defects in SiN layer in MONOS-type memories on the basis of the first-principles calculations. We find that SiN structures with a hydrogen impurity tend to reveal reversible structural change during program/erase operation.

An advantage of an RLD (reconfigurable logic device) such as an FPGA (field programmable gate array) is that it can be customized after being manufactured. Due to the aggressive technology scaling, device density is increasing, and it has become a serious problem in power consumption accordingly. In SoC of embedded systems, power gating is one of the major power reduction techniques. However, it is difficult to adopt SRAM-based RLDs because of the high overhead and SRAM being volatile. In this paper, we describe a TEG (test element group) chip of a reconfigurable logic based FeRAM (ferroelectric random access memory) technology. FeRAM brings reconfigurable logic devices the advantage of being a genuine power gater. The chip employs island-style routing architecture and uses a variable grain logic cell as a logic block. A NV-FF (non-volatile flip-flop), which contains FeRAM, a FF, and power-gating control circuits, is used as both configuration memories and FFs in a logic block. The NV-FF can transmit data between FeRAM and FF automatically when a power source is turned off/on. Thus chip-level power gating is possible. The hibernate/restore time is less than 1 ms. The chip has 1818 logic blocks and an area of 54.76 mm2.

In this paper, the performance of the induced dimension reduction (IDR) method implemented along with the method of moments (MoM) is described. The MoM is based on a combined field integral equation for solving large-scale electromagnetic scattering problems involving conducting objects. The IDR method is one of Krylov subspace methods. This method was initially developed by Peter Sonneveld in 1979; it was subsequently generalized to the IDR(s) method. The method has recently attracted considerable attention in the field of computational physics. However, the performance of the IDR(s) has hardly been studied or practiced for electromagnetic wave problems. In this study, the performance of the IDR(s) is investigated and clarified by comparing the convergence property and memory requirement of the IDR(s) with those of other representative Krylov solvers such as biconjugate gradient (BiCG) methods and generalized minimal residual algorithm (GMRES). Numerical experiments reveal that the characteristics of the IDR(s) against the parameter s strongly depend on the geometry of the problem; in a problem with a complex geometry, s should be set to an adequately small value in order to avoid the "spurious convergence" which is a problem that the IDR(s) inherently holds. As for the convergence behavior, we observe that the IDR(s) has a better convergence ability than GPBiCG and GMRES(m) in a variety of problems with different complexities. Furthermore, we also confirm the IDR(s)'s inherent advantage in terms of the memory requirements over GMRES(m).

This paper presents flexible inner-outer Krylov subspace methods, which are implemented using the fast multipole method (FMM) for solving scattering problems with mixed dielectric and conducting object. The flexible Krylov subspace methods refer to a class of methods that accept variable preconditioning. To obtain the maximum efficiency of the inner-outer methods, it is desirable to compute the inner iterations with the least possible effort. Hence, generally, inaccurate matrix-vector multiplication (MVM) is performed in the inner solver within a short computation time. This is realized by using a particular feature of the multipole techniques. The accuracy and computational cost of the FMM can be controlled by appropriately selecting the truncation number, which indicates the number of multipoles used to express far-field interactions. On the basis of the abovementioned fact, we construct a less-accurate but much cheaper version of the FMM by intentionally setting the truncation number to a sufficiently low value, and then use it for the computation of inaccurate MVM in the inner solver. However, there exists no definite rule for determining the suitable level of accuracy for the FMM within the inner solver. The main focus of this study is to clarify the relationship between the overall efficiency of the flexible inner-outer Krylov solver and the accuracy of the FMM within the inner solver. Numerical experiments reveal that there exits an optimal accuracy level for the FMM within the inner solver, and that a moderately accurate FMM operator serves as the optimal preconditioner.

In disk-based storage systems, non-volatile write caches have been widely used to reduce write latency as well as to ensure data consistency at the level of a storage controller. Write cache policies should basically consider which data is important to cache and evict, and they should also take into account the real I/O features of a non-volatile device. However, existing work has mainly focused on improving basic cache operations, but has not considered the I/O cost of a non-volatile device properly. In this paper, we propose a pattern-aware write cache policy, PAW for a NAND flash memory in disk-based mobile storage systems. PAW is designed to face a mix of a number of sequential accesses and fewer non-sequential ones in mobile storage systems by redirecting the latter to a NAND flash memory and the former to a disk. In addition, PAW employs the synergistic effect of combining a pattern-aware write cache policy and an I/O clustering-based queuing method to strengthen the sequentiality with the aim of reducing the overall system I/O latency. For evaluations, we have built a practical hard disk simulator with a non-volatile cache of a NAND flash memory. Experimental results show that our policy significantly improves the overall I/O performance by reducing the overhead from a non-volatile cache considerably over a traditional one, achieving a high efficiency in energy consumption.

An alternative design for constructing multilevel space-time codes is proposed. For a given space-time block code, we combine several component codes in conjunction with set partitioning of the expanded signal constellation according to the coding gain distance criterion. The error performance of an example code is compared with a traditional multilevel space-time code in computer simulation.

For tactile feedback in mobile devices, the size and the power consumption of tactile modules are the dominant factors. Thus, vibration motors have been widely used in mobile devices to provide tactile sensation. However, the vibration motor cannot sufficiently generate a great amount of tactile sensation because the magnitude and the frequency of the vibration motor are coupled. For the generation of a wide variety of tactile sensations, this paper presents a new tactile actuator that incorporates a solenoid, a permanent magnet and an elastic spring. The feedback force in this actuator is generated by elastic and electromagnetic force. This paper also proposes a tiny tactile module with the proposed actuators. To construct a tiny tactile module, the contactor gap of the module is minimized without decreasing the contactor stroke, the output force, and the working frequency. The elastic springs of the actuators are separated into several layers to minimize the contactor gap without decreasing the performance of the tactile module. Experiments were conducted to investigate each contactor output force as well as the frequency response of the proposed tactile module. Each contactor of the tactile module can generate enough output force to stimulate human mechanoreceptors. As the contactors are actuated in a wide range of frequency, the proposed tactile module can generate various tactile sensations. Moreover, the size of the proposed tactile module is small enough to be embedded it into a mobile device, and its power consumption is low. Therefore, the proposed tactile actuator and module have good potential in many interactive mobile devices.

Due to the detachability of Flash storage, which is a dominant portable storage, data integrity stored in Flash storages becomes an important issue. This study considers the performance of Flash Translation Layer (FTL) schemes embedded in Flash storages in conjunction with file system behavior that pursue high data integrity. To assure extreme data integrity, file systems synchronously write all file data to storage accompanying hot write references. In this study, we concentrate on the effect of hot write references on Flash storage, and we consider the effect of absorbing the hot write references via nonvolatile write cache on the performance of the FTL schemes in Flash storage. In so doing, we quantify the performance of typical FTL schemes for a realistic digital camera workload that contains hot write references through experiments on a real system environment. Results show that for the workload with hot write references FTL performance does not conform with previously reported studies. We also conclude that the impact of the underlying FTL schemes on the performance of Flash storage is dramatically reduced by absorbing the hot write references via nonvolatile write cache.

Dynamically Programmable Gate Arrays (DPGAs) provide more area-efficient implementations than conventional Field Programmable Gate Arrays (FPGAs). One of typical DPGA architectures is multi-context architecture. An DPGA based on multi-context architecture is Multi-Context FPGA (MC-FPGA) which achieves fast switching between contexts. The problem of the conventional SRAM-based MC-FPGA is its large area and standby power dissipation because of the large number of configuration memory bits. Moreover, since SRAM is volatile, the SRAM-based multi-context FPGA is difficult to implement power-gating for standby power reduction. This paper presents an area-efficient and nonvolatile multi-context switch block architecture for MC-FPGAs based on a ferroelectric-capacitor functional pass-gate which merges a multiple-valued threshold function and a nonvolatile multiple-valued storage. The test chip for four contexts is fabricated in a 0.35 µm-CMOS/0.60 µm-ferroelectric-capacitor process. The transistor count of the proposed multi-context switch block is reduced to 63% in comparison with that of the SRAM-based one.