Akio ICHIKAWA Takashi TSUSHIMA Toshiyuki YOSHIDA Yoshinori SAKAI
This paper proposes a bitstream scaling technique for MPEG video for the purpose of media synchronizations. The proposed scaling technique can reduce the frame rate as well as the bit rate of an MPEG data sequence to fit them to the values specified by a synchronization system. The advantage of the proposed technique over existing scaling methods is that it is considering not only the performance of synchronization but also the picture quality of the resulting sequences. To further improve the quality of sequences scaled by the proposed method, this paper also proposes an MPEG encoding technique which sets some of the parameters suitable for the scaling. An experiment using these techniques in an actual media synchronization system has illustrated the usefulness of the proposed approach.
Akiko NAKANIWA Hiroyuki EBARA Hiromi OKADA
In this paper, we study the optimal allocation of multimedia files in distributed network systems. In these systems, the files are shared by users connected with different servers geographically separated, and each file must be stored in at least one of servers. Users can access any files stored in any servers connected with high-speed communication networks. Copies of the files accessed frequently are to be stored in several servers that have databases. So, it is one of the most important problems how to assign the files to servers in view of costs and delays. Considering these problems in heterogeneous network environments, we present a new system model that covers wide range of multimedia network applications like VOD, CALS, and so on. In these systems, it is obvious that there is trading-off relationship between costs and delays. Our objective is to find the optimal file allocation such that the total cost is minimized subject to the total delay. We introduce a 0-1 integer programming formulation for the optimization problem, and find the optimal file allocation by solving these formulae.
By sacrificing approximately ten percent of the transmission speed, ultra-high speed optical time division multiplexed network can be fully operatable by the use of currently available electrical switches. The network utilizes dispersion managed quasi-solitons and transmits TDM packet which comprises of ATM cells that are introduced from a gateway through bit compression to match to the ultra-high speed traffics. The network can provide flexible bandwidth and bit on demand at burst rate of the maximum LAN speed.
Toshiyuki YOSHIDA Yoshinori SAKAI
The authors have proposed a design method for two-dimensional (2-D) separable-denominator (SD) periodically time-variant digital filters (PTV DFs) and confirmed their superiority over 2-D time-invariant DFs. In that result, the periodicity matrix representing the periodicity of the varying filter coefficients is, however, restricted to two cases. This paper extends that idea so that the input-output relation of 2-D SD PTV DFs with an arbitrary periodicity matrix can be determined. This enables us to design wide range of 2-D PTV DFs.
Akihiro SHIMIZU Tsutomu HORIOKA Hirohito INAGAKI
A password authentication method PERM has been developed for application to e-mail forwarding. This method is suitable for communications in insecure network environments such as the Internet. In particular, it can be adapted to Internet appliances and Java applets which have limited performance. The PERM method does not require password resettings and enables high-speed authentication processing with a small-sized program. Moreover, it does not use facilities or mechanisms for generating random numbers and writing them into and reading them out of an IC card or similar storage medium on the user's side.
Yoshiaki HORI Hidenari SAWASHIMA Hideki SUNAHARA Yuji OIE
On wide area networks (WANs), UDP has likely been used for real-time applications, such as video and audio. UDP supplies minimized transmission delay by omitting the connection setup process, flow control, and retransmission. Meanwhile, more than 80 percent of the WAN resources are occupied by Transmission Control Protocol (TCP) traffic. As opposed to UDP's simplicity, TCP adopts a unique flow control mechanism with sliding windows. Hence, the quality of service (QoS) of real-time applications using UDP is affected by TCP traffic and its flow control mechanism whenever TCP and UDP share a bottleneck node. In this paper, the characteristics of UDP packet loss are investigated through simulations of WANs conveying UDP and TCP traffic simultaneously. In particular, the effects of TCP flow control on the packet loss of real-time audio are examined to discover how real-time audio should be transmitted with the minimum packet loss, while it is competing with TCP traffic for the bandwidth. The result obtained was that UDP packet loss occurs more often and successively when the congestion windows of TCP connections are synchronized. Especially in this case, the best performance of real-time audio applications can be obtained when they send-small sized packets without reducing their transmission rates.
Lan CHEN Susumu YOSHIDA Hidekazu MURATA Shouichi HIROSE
Personal communication systems are increasingly required to accommodate not only voice traffic, but also various types of data traffic. Generally speaking, voice traffic is symmetric between uplink and downlink, while data traffic can be highly asymmetric. It is therefore inefficient to accommodate data in a conventional TDMA/TDD system with fixed TDD boundary. In this paper, focusing on the continuous data traffic which requires multi-slots in a circuit based TDMA/TDD system, an algorithm is proposed in which the TDD boundary are moved adaptively to accommodate data traffic efficiently. Comparing with the boundary-fixed conventional algorithm, computer simulations confirm that the proposed algorithm has superior performance in the excessive transmission delay of data while maintaining the performance of voice. The intercell interference between mobiles due to different TDD boundaries is also confirmed to be negligible. Moreover, almost the similar performance improvements of the proposed algorithm are confirmed for two different average message sizes of data calls.
This paper proposes an adaptive permission probability control method for the CDMA/PRMA access protocol. The proposed method is effective to the uplink channels of the integrated voice and data wireless system. The proposed method uses the R-ALOHA protocol with end-of-use flags in order to avoid the reservation cancellations caused by excessive multiple-access interference. Also, a higher priority at packet transmission is given to voice compared with data so that the real-time transmission of voice packets can be guaranteed. Priority is controlled by suitably varying permission probabilities. Permission probabilities are adaptively calculated according to both the channel load and the channel capacities. The usefulness of this proposed method is ensured through computer simulation in an isolated cell environment. Moreover, various applications to cellular environments are investigated. The calculated results indicate that transmission efficiency has been improved compared with the conventional CDMA/PRMA protocol.
This paper presents a novel transmission diversity scheme for code division multiple access system. Conventional diversity receivers in mobile stations require space and complicated circuits, however, the proposed diversity schemes present significant diversity effect without any diversity equipment at the mobile station. It is possible to use the transmitter diversity at the base station by using the feature of time division duplex (TDD) which has strongly correlated fading patterns in both forward and reverse link. Computer simulation is performed to evaluate the performance of the proposed systems for single user environment. The performance of the system 1, which select best situated antenna, is analyzed and the BER performance for multiple access is presented.
Eiji OKI Naoaki YAMANAKA Kohei SHIOMOTO Soumyo D. MOITRA
This paper proposes a multiple QoS control scheme that combines the head-of-line priority (HOLP) discipline with equivalent-window connection admission control (CAC). The proposed scheme can support the different cell loss ratios of both delay-sensitive traffic in high-priority buffers and delay-tolerant traffic in low-priority buffers. The CAC scheme extends a measurement-based CAC algorithm for a single buffer to the low-priority buffer with the HOLP discipline to provide the cell loss ratio objective. We introduce an equivalent window for monitoring low-priority cell streams. The equivalent window size equals the period within which the number of times the low-priority buffer is scanned to read cells is constant. Thus the equivalent window size varies with the high-priority queueing state. Numerical results indicate that the proposed QoS control scheme using the equivalent-window CAC can utilize network resources more effectively than the conventional control scheme which is Virtual Path (VP) separation for different cell loss requirement services. In addition, it is confirmed that the proposed scheme provides conservative admissible loads. Thus, this proposed scheme can achieve large statistical gains while providing both high-priority and low-priority cell loss ratio objectives. The proposed scheme will be very useful for cost-effective multimedia services that have different QoS requirements.
Qi-Wei GE Hidenori YANAGIDA Kenji ONAGA
A data-flow program net is a graph representation of data-flow programs consisting of three types of nodes, AND-node, OR-node and SWITCH-node, which represent arithmetic/logical, data merge and context switch operations respectively. Minimum firing (completion) time T of a program net is an important element in computing parallel degree PARAdeg residing in a data-flow program and is defined as the minimum time when the program net is executed by enough many processors. In this paper, we propose algorithms to efficiently compute T by contracting AND-nodes generally for self-cleaning SWITCH-less program nets with arbitrary node firing time and give the experimental results of the algorithms to show the efficiency.
Nozomu TOGAWA Masao YANAGISAWA Tatsuo OHTSUKI
This paper proposes a fast scheduling algorithm based on gradual time-frame reduction for datapath synthesis of digital signal processing hardwares. The objective of the algorithm is to minimize the costs for functional units and registers and to maximize connectivity under given computation time and initiation interval. Incorporating the connectivity in a scheduling stage can reduce multiplexer counts in resource binding. The algorithm maximizes connectivity with maintaining low time complexity and obtains datapath designs with totally small hardware costs in the high-level synthesis environment. The algorithm also resolves inter-iteration data dependencies and thus realizes pipelined datapaths. The experimental results demonstrate that the proposed algorithm reduces the multiplexer counts after resource binding with maintaining low costs for functional units and registers compared with eight conventional schedulers.
Kei EGUCHI Takahiro INOUE Akio TSUNEDA
In this paper, an FPGA (Field Programmable Gate Array)-implementable digital chaos circuit with nonlinear mapping function learning ablility is proposed. The features of this circuit are user-programmability of the mapping functions by on-chip supervised learning, robustness of chaos signal generation based on digital processing, and high-speed and low-cost thanks to its FPGA implementation. The circuit design and analysis are presented in detail. The learning dynamics of the circuit and the quantitization effect to the quasi-chaos generation are analyzed by numerical simulations. The proposed circuit is designed by using an FPGA CAD tool, Verilog-HDL. This confirmed that the one-dimensional chaos circuit block (except for SRAM's) is implementable on a single FPGA chip and can generate quasi-chaos signals in real time.
Kei EGUCHI Takahiro INOUE Akio TSUNEDA
In this letter, a digital circuit realizing a Rossler model is proposed. The proposed circuit features exact reproducibility of chaos signals which is desired in chaos-based communication systems. By employing an FPGA implementation, the proposed circuit can achieve high-speed and low-cost realization. The chaotic behavior of the quasi-chaos of the proposed circuit is analyzed by numerical simulations. To confirm the validity of the FPGA implementation, the proposed circuit is designed by using an FPGA CAD tool, Verilog-HDL. This circuit design showed that the proposed circuit can be implemented onto a single FPGA and can realize real-time chaos generation.
Sirirat TREETASANATAVORN Toshiyuki YOSHIDA Yoshinori SAKAI
In this paper, we propose an idea for intramedia synchronization control using a method of end-to-end delay monitoring to estimate future delay in delay compensation protocol. The estimated value by Kalman filtering at the presentation site is used for feedback control to adjust the retrieval schedule at the source according to the network conditions. The proposed approach is applicable for the real time retrieving application where `tightness' of temporal synchronization is required. The retrieval schedule adjustment is achieved by two resynchronization mechanisms-retrieval offset adjustment and data unit skipping. The retrieval offset adjustment is performed along with a buffer level check in order to compensate for the change in delay jitter, while the data unit skipping control is performed to accelerate the recovery of unsynchronization period under severe conditions. Simulations are performed to verify the effectiveness of the proposed scheme. It is found that with a limited buffer size and tolerable latency in initial presentation, using a higher efficient delay estimator in our proposed resynchronization scheme, the synchronization performance can be improved particularly in the critically congested network condition. In the study, Kalman filtering is shown to perform better than the existing estimation methods using the previous measured jitter or the average value as an estimate.
Doo Seop EOM Masashi SUGANO Masayuki MURATA Hideo MIYAHARA
In the wireless ATM network, the key issue is to guarantee various QoS (Quality of Service) under the conditions of the limited radio link bandwidth and error prone characteristics. In this paper, we show a combination method of the error correction schemes, which is suitable to establish multimedia wireless ATM Networks while keeping an efficient use of the limited bandwidth. We consider two levels of FEC; a bit-level and a cell-level to guarantee cell loss probabilities of real time applications. By combining two levels of FEC, various requirements on cell loss can be met. We then apply the bit-level FEC and ARQ protocol for the data communication; tolerant to the delay characteristics. Through the analytical methods, the required overheads of FECs are examined to satisfy the various QoS requirements of CBR connections. The mean delay analysis for the UBR service class is also presented. In numerical examples, we show how the combination scheme to guarantee various cell loss requirements affects the call blocking probability of the CBR service class and the delay of UBR service class.
This paper proposes a new design method of a nonlinear filtering algorithm in continuous-time stochastic systems. The observed value consists of nonlinearly modulated signal and additive white Gaussian observation noise. The filtering algorithm is designed based on the same idea as the extended Kalman filter is obtained from the recursive least-squares Kalman filter in linear continuous-time stochastic systems. The proposed filter necessitates the information of the autocovariance function of the signal, the variance of the observation noise, the nonlinear observation function and its differentiated one with respect to the signal. The proposed filter is compared in estimation accuracy with the MAP filter both theoretically and numerically.
The asymptotic behavior of the recurrence time with fidelity criterion is discussed. Let X= be a source and Y= a database. For a Δ>0 and an integer l>0 define (Y,X,Δ) as the minimum integer N satisfying dl(,) Δ subject to a fidelity criterion dl. In this paper the following two i. i. d. cases are considered: (A) Xi P and Yi Q, where P and Q are probability distributions on a finite alphabet, and (B) Xi N(0,1) and Yi N(0,1). In case (A) it is proved that (1/l)log2(Y,X,Δ) almost surely converges to a certain constant determined by P, Q and Δ as l. The Kac's lemma plays an important role in the proof on the convergence. In case (B) it is shown that there is a quantity related to (1/l)log2 (Y,X,Δ) that converges to the rate-distortion bound in almost sure sense.
This paper proposes polling-based real-time software for MPEG2 System protocol LSIs, which is a typical embedded and real-time system on a chip, and demonstrates its performance and usefulness. The polling-based real-time software is designed and optimized by analyzing application specific function requirements and deciding scheduling intervals and the execution cycles of each task. It requires neither hardware for multiple interrupt handling nor software for heavy context switching. The polling-based approach provides sufficient performance without any hardware and software overhead for a real-time application like the MPEG2 System protocol.
Shunichi ISHIWATA Takayasu SAKURAI
Media processors have emerged so that a single LSI can realize multiple multimedia functions, such as graphics, video, audio and telecommunication with effectively shared hardware and flexible software. First, the difference between media processors and general-purpose microprocessors with multimedia extensions is clarified. Features for processes and data in the multimedia applications are summarized and are followed by the multimedia enhancements that the recent general-purpose microprocessors use. The architecture for media processors reflects the further optimized utilization of these features and realizes better price-performance ratio than the general-purpose microprocessors. Finally, the future directions of media processors are estimated, based on the performance, the power dissipation and the die size of the present microprocessors with multimedia extensions and the present media processors. The demand to improve the price-performance ratio for the whole system and to reduce the power consumption makes the media processor evolve into a system processor, which integrates not only the media processor but also the function of a general-purpose microprocessor, various interfaces and DRAMs.