The lock-up time of a PLL frequency synthesizer mainly depends on the total loop gain. Since the gain of the conventional phase detector is constant, it is difficult to improve the lock-up time by the phase detector. In this paper, we reconsider the operation of the phase detector and propose the PLL frequency synthesizer with multi-phase detector in which the gain of phase detector is increased by using four stage phase detectors and charge pumps. Then, a higher speed lock-up time and good spurious characteristics can be achieved.

This paper describes low-power architecture-methodologies for programmable multimedia processors, which will become major functional units in System-On-a-Chip. After brief review on multimedia processing and low-power considerations, recent programmable chips, including MPUs and DSPs, are investigated in terms of low-power implementation. In order to show the difference of the low-power approaches between programmable processors and ASIC processors, a single-chip MPEG-2 encoder is also included as an example of ASIC design.

Recent work in the area of ultrafast optical time-division multiplexed (OTDM) networking at MIT Lincoln Laboratory is presented. A scalable helical local area network or HLAN architecture, presented elsewhere as an architecture well-suited to ultrafast OTDM LANs and MANs, is considered in the context of wide area networking. Two issues arise in scaling HLAN to the wide area. The first is protocol extension, and the second is supporting the required bandwidth on the long-haul links. In this paper we discuss these challenges and describe progress made in both architecture and technologies required for scaling HLAN to the wide area.

Recent work in the area of ultrafast optical time-division multiplexed (OTDM) networking at MIT Lincoln Laboratory is presented. A scalable helical local area network or HLAN architecture, presented elsewhere as an architecture well-suited to ultrafast OTDM LANs and MANs, is considered in the context of wide area networking. Two issues arise in scaling HLAN to the wide area. The first is protocol extension, and the second is supporting the required bandwidth on the long-haul links. In this paper we discuss these challenges and describe progress made in both architecture and technologies required for scaling HLAN to the wide area.

This paper describes a new reconfigurable processor architecture called REMARC (Reconfigurable Multimedia Array Coprocessor). REMARC is a small array processor that is tightly coupled to a main RISC processor. It consists of a global control unit and 64 16-bit processors called nano processors. REMARC is designed to accelerate multimedia applications, such as video compression, decompression, and image processing. These applications typically use 8-bit or 16-bit data therefore, each nano processor has a 16-bit datapath that is much wider than those of other reconfigurable coprocessors. We have developed a programming environment for REMARC and several realistic application programs, DES encryption, MPEG-2 decoding, and MPEG-2 encoding. REMARC can implement various parallel algorithms which appear in these multimedia applications. For instance, REMARC can implement SIMD type instructions similar to multimedia instruction extensions for motion compensation of the MPEG-2 decoding. Furthermore, the highly pipelined algorithms, like systolic algorithms, which appear in motion estimation of the MPEG-2 encoding can also be implemented efficiently. REMARC achieves speedups ranging from a factor of 2.3 to 21.2 over the base processor which is a single issue processor or 2-issue superscalar processor. We also compare its performance with multimedia instruction extensions. Using more processing resources, REMARC can achieve higher performance than multimedia instruction extensions.

In this paper, we introduce a processor called Media Core Processor (MCP), which targets a system solution for consumer multimedia products. MCP is a heterogeneous multi-processor system designed to guarantee full frame MPEG decoding, and to reduce power consumption. In our processor architecture, each processing unit is optimized to support various characteristics of media processing. All processing units work in parallel in a macro-pipeline manner, thereby achieving high utilization of the processing units. A performance evaluation shows that audio/video full-frame decoding can be realized on 54 MHz operating frequency without any support from external hardware or a CPU. In addition, the high programmability of the MCP provides flexibility and reduces the time-to-market.

This paper describes a way of implementing a conceptual model for temporal data on a commercial object database system. The implemented version is provided as a class library. The library enables applications to handle temporal data. Any application can employ the library because it does not depend on specific applications. Furthermore, we propose an enhanced version of Time Index. The index efficiently processes event queries in particular. These queries search time intervals in which given events are all valid. We also investigate the effectiveness of the enhanced Time Index.

Informally, private information retrieval for k 1 databases (k-PIR) is an interactive scheme that enables a user to make access to (separated) k replicated copies of a database and privately retrieve any single bit out of the n bits of data stored in the database. In this model, "privacy" implies that the user retrieves the bit he is interested in but releases to each database nothing about which bit he really tries to get. Chor et. al. proposed 2-PIR with communication complexity 12 n1/32 that is based on the covering codes. Then Ambainis recursively extended the scheme by Chor et. al. and showed that for each k 2, there exists k-PIR with communication complexity at most ckn1/(2k-1) some constant ck > 0. In this paper, we relax the condition for the covering codes and present time-efficient 2-PIR with communication complexity 12 n1/3. In addition, we generally formulate the recursive scheme by Ambainis and show that for each k 4, there exists k-PIR with communication complexity at most ck' n1/(2k-1) for some constant ck' << ck.

This paper surveys recent research activities on three major areas of digital media information base, namely, video database systems as a typical example of temporal application, database systems for mixed reality as an instance of spatial application, and kansei management for digital media retrieval as a case of humanistic feelings application. Current research results by the project Advanced Database Systems for Integration of Media and User Environments are reported.

Support of collaborative work and management of spatio-temporal data has become one of the most interesting and important database applications, which is due to the tremendous progress of database and its surrounding technologies in the last decade. In this paper, we investigate the new generation database technologies that are needed to support such advanced applications. Because of the recent progress of virtual reality technology, virtual work spaces are now available. We examine a typical CSCW (Computer Supported Cooperative Work) fsystem to identify database problems that arise from it. We introduce typical approaches to database improvement based on the high-level view and the virtual reality technique. Also, in this paper, the following are introduced and discussed: the design and implementation of three- and four-dimensional spatio-temporal database systems, VRML (Virtual Reality Modeling Language) database systems, fast access methods to spatio-temporal data, and the interval-based approach to temporal multimedia databases.

This paper describes a new floating-point divider (FDIV), in which the key features of redundant binary circuits and an asynchronous clock scheme reduce the delay time and area penalty. The redundant binary representation of +1 = (1, 0), 0 = (0, 0), -1 = (0,1) is applied to the all mantissa division circuits. The simple and unified representation reduces circuit delay for the quotient determination. Additionally, the local clock generator circuit for the asynchronous clock scheme eliminates clock margin overhead. The generator circuit guarantees the worst delay-time operation by the feedback loop of the replica delay paths via a C-element. The internal iterative operation by the asynchronous scheme and the modified redundant-binary addition/subtraction circuit keep the area small. The architecture design avoids extra calculation time for the post processes, whose main role is to produce the floating-point status flags. The FDIV core using proposed technologies operates at 42. 1 ns with 0.35 µm CMOS technology and triple metal interconnections. The small core of 13.5 k transistors is laid-out in a 730µm 910 µm area.

This paper studies the problem of testing concurrent systems considered as blackboxes and specified using asynchronous Communicating Finite State Machines. We present an approach to derive test cases for concurrent systems in a succinct and formal way. The approach addresses the state space explosion problem by introducing a causality relation model and the concept of logical time to express true concurrency and describe timing constraints on events. The conformance relation between test cases and trace observed from the real system is defined, and a new test architecture as well as a test case application is presented according to the conformance relation defined. To improve verdict capability of test cases, the approach is enhanced by relaxing the unit-time assumption to any natural number. And a computationally efficient algorithm for the enhanced approach is presented and the algorithm is evaluated in terms of computational efficiency and verdict capability. Finally the approach is generalized to describe timing constraints by any real numbers.

The time-memory trade-off cryptanalysis for block ciphers with a search space of size 2N (N: key length) cannot achieve a success probability excceding 63%. This is caused by some unavoidable overlapping of keys in the space. For elavating the success probability of finding the correct key, a larger search space is necessary. That is, the increase of time complexity for precomputation would be inevitable. This paper theoretically shows, however, no further price is required for the size of look-up tables for the number of encryptions for searching for the key that matches the given ciphertext - plaintext pairs. This theory is confirmed by some empilical results.

Rate monotonic traffic scheduling algorithm had been shown to be the optimal static priority assignment scheme. The system model studied in can be considered (although not realistic) as a preemptive multiplexer which accepts constant bit rate connections that generate packets periodically. The multiplexer adopts a service discipline such that a lower priority packet can be preempted at any stage by a higher priority one without any loss. The constraint is that every packet has to complete its service before the arrival of its succeeding packet generated by the same connection. In this paper, we study the schedulability problem of rate monotonic schedulers for a fixed-length packet switched network such as the ATM network. A necessary and sufficient condition for a set of m constant bit rate connections to be rate monotonic schedulable is first derived and then utilized to design fast admission control algorithms. One of our algorithms computes in advance the minimum period of a connection which can be accepted given a set of existing connections.

IEEE 802. 11 is a standard for wireless LANs. The basic access method in its MAC layer protocol is the distributed coordination function (DCF) for the ad hoc networks. It is based on the mechanism of carrier sense multiple access with collision avoidance (CSMA/CA). DCF is used to support asynchronous data transmission. However, frames in DCF do not have priorities, making it unsuitable for real-time applications. With a little bad luck, a station might have to wait arbitrarily long to send a frame. In this paper, we propose a method to modify the CSMA/CA protocol such that station priorities can be supported. The method is simple, efficient and easy to implement in comparison to point coordination function (PCF), another access method in IEEE 802. 11 based on access points (base stations). Simulations are conducted to analyze the proposed scheme. The results show that DCF is able to carry the prioritized traffic with the proposed scheme.

The influence of loaded capacitance on the resonant frequency of a triplate-type strip resonator is investigated through numerical simulations by means of the finite-difference time-domain (FDTD) method. This type of resonator is one of the basic components of very small high-dielectric stripline filters, named laminated planar filters. Numerical results of resonant frequencies are compared with experimental results and found to be in excellent agreement, which circumstance ensures that the FDTD method can be applied to the characterization of a wide range of laminated planar microwave devices including resonators and filters. It is also found that the resonant frequency is directly related to the square root of its line capacitance when the resonator is regarded equivalently as a series LC circuit.

In this paper, we propose a test methodology for core-based system LSIs. Our test methodology aims to decrease testing time for core-based system LSIs. In our method, every core is supplied with several sets of test vectors. Every set of test vectors guarantees sufficient fault coverage. Each set of test vectors consists of two parts. One is based on built-in self-test (BIST) and the other is based on external testing. These sets of test vectors are designed to have different ratio of BIST to external testing each other for every core. We can minimize testing time for core-based system LSIs by selecting from the given sets of test vectors for each core. The main contributions of this paper are summarized as follows. (i) BIST is efficiently combined with external testing to relax the limitation of the external primary inputs and outputs. (ii) External testing for one of cores and BISTs for the others are performed in parallel to reduce the total testing time. (iii) The testing time minimization problem for core-based system LSIs is formulated as a combinatorial optimization problem to select the optimal set of test vectors from given sets of test vectors for each core.

We have proposed an algorithm to apply perfectly matched layer (PML) absorbing boundary condition to the noncubic cell time-domain method. The extended method has a merit of flexibility in truncating the computational domain by the use of a curvilinear PML. In this paper we apply a circular PML for computing the scattered fields of a dielectric cylinder or cylindrical shell of arbitrary cross section shape. Numerical results are presented to demonstrate the accuracy of this method.

This paper proposes a method to reduce the context switching time using a register bank to store contexts of working tasks. Hardware cost and performance were measured by modeling the register bank and controller in VHDL. Following results were obtained: (1) The controller can be implemented with a much smaller amount of hardware cost compared to that of the register bank, which is realized by SRAM module. (2) Context switching time can be reduced to less than 50% compared to that by software implementation. (3) Combination of the proposed architecture with our previous work (RTOS implemented in HW) gives us much higher performance of a hard real-time system.

This paper proposes a novel signal transmission scheme for helicopter satellite communications. The proposed scheme is based on time diversity, and combined with a novel algorithm to suppress an influence of carrier phase slip. In the proposed scheme, carrier phase slip is detected in cross correlation processing of the received signal, and is effectively suppressed. The proposed scheme thus makes it possible to employ coherent phase shift keying modulation to achieve bit error rate performance superior to that of differential phase shift keying modulation even in the low carrier-to-noise power ratio environment.