This paper studies congestion control schemes for integrated variable bit-rate (VBR) video and data communications, where the quality of service (QOS) of each medium needs to be satisfied. In order to control congestion, we exert here either dynamic resolution control or QOS control. The dynamic resolution control scheme in this paper dynamically changes the temporal or spatial resolution of video according to the network loads. The QOS control scheme here assigns a constant capacity of buffer to each connection and determines the video resolution in order to guarantee the QOS of each medium at the connection establishment. The performance of these schemes is evaluated through simulation in terms of throughput, video frame delay probability distribution, and video frame loss rate. We also examine the effects of priority scheduling and packet discarding on the performance. Numerical results indicate that both dynamic resolution and QOS control attain low delay jitters as well as large video and data throughput. In particular, the QOS control is shown to be more suitable for integrated VBR video and data communications.

In this paper, the ATM Mini-Bar System (AMBS) which is a future information providing service infrastructure is proposed. The purpose of AMBS is to provide a multi-media environment in which a user can (1) select and get quickly any needed information, in low cost, at any time, among very large amount of different media information provided by a variety of providers, (2) be charged only for the information which is selected and used, (3) edit or process informations into users' individually requested style or format before using them. The basic concept and configurations of AMBS are also addressed. This system is basically a center-end oriented one-way information providing system. The information center broadcasts its contents to all user equipments based on a user request forecast, and every user equipment stores the delivered contents in its large storage. A user can select one's needed informations from the storage, and may edit or process them within the user equipment. The charge is only on the read informations from the storage, not on all contents in it. The key points of this system are the following three. (A) Introduction of a broadcast (or multicast) media for economical information delivery (exactly speaking, it is a predelivery which means a delivery before request) to user equipments. (B) Introduction of a 1 to 1 communication network for selective charging and control of each user equipments. (C) Introduction of the user equipment storage for Quick response to user information request in most cases with the broadcast (or multicast) information delivery media described above, Separation of information delivery speed and replay speed to increase system flexibility, Local user information processing or editing. As an example of technical solutions, a memory architecture, which is based on hierarchical architecture, is described. AMBS is expected to give some impacts to information industries because it can integrate many kinds of services into the same platform, but some standerdization items are needed to realize it.

The paper ptoposes a method to synthesize low-power control-logic modules by combining transistor-size optimization and transistor layout. Transistor sizing and layout work synergistically to achieve power/area optimization. Transistor size minimization provides more spaces for layout to be compacted. Layout compaction results in shorter wire length (i.e. smaller load capacitance), which allows transistors to become smaller. The details of transistor sizing and layout compaction are also described. When applied to circuits with up to 10,000 transistors, the optimizer reduced the average transistor size to one eighth while maintaining the same delay. The power dissipation is cut to half even when wiring capacitances are dominant.

A uniquely-structured Usage Parameter Control (UPC) method named Virtual-shaping is proposed which considers cell arrival time jitter between user and UPC point. The method uses a modified Dangerous Bridge UPC circuit (Sliding window type) and virtually (logically) shapes cell traffic using cell arrival time compensation to offset cell delay variation (CDV). In addition, the proposed method is based on a cell-buffer-less structure and can be realized with reasonable hardware. The method yields precise and accurate monitoring. Computer simulations show that the method offers higher network utilization than the conventional Leaky Bucket based UPC method. The proposed method will make it possible to create more effective B-ISDNs, and more cost-effective broadband VBR services.

This paper surveys low-power circuit techniques for CMOS ULSIs. For many years a power supply voltage of 5 V was employed. During this period power dissipation of CMOS ICs as a whole increased four-fold every three years. It is predicted that by the year 2000 the power dissipation of high-end ICs will exceed the practical limits of ceramic packages, even if the supply voltage can be feasibly reduced. CMOS ULSIs now face a power dissipation crisis. A new philosophy of circuit design is required. The power dissipation can be minimized by reducing: 1) supply voltage, 2) load capacitance, or 3) switching activity. Reducing the supply voltage brings a quadratic improvement in power dissipation. This simple solution, however, comes at a cost in processing speed. We investigate the proposed methods of compensating for the increased delay at low voltage. Reducing the load capacitance is the principal area of interest because it contributes to the improvement of both power dissipation and circuit speed. Pass-transistor logic is attracting attention as it requires fewer transistors and exhibits less stray capacitance than conventional CMOS static cicuits. Variations in its circuit topology as well as a logic synthesis method are presented and studied. A great deal of research effort has been directed towards studying every portion of LSI circuits. The research achievements are categorized in this paper by parameters associated with the source of CMOS power dissipation and power use in a chip.

A new approach which implements a simple, high-speed phase detector with precharge logic will be presented. The minimum detectable phase difference is 40 psec, which is less than a half of conventional detectors. A current mode ring oscillator with a complementary-input bias generator has also been developed to enhance the dynamic range of the VCO under a low supply voltage. A fully CMOS PLL was designed using 0.5-µm technology. By virtue of this simple, fast detector, the wide operation range of 250 MHz at 1.5 V to 622 MHz at 3.0 V was achieved by simulation.

Recent advances of processing speed and window systems in computers, especially workstations, accelerate multi-media data processing (MMDP). Then, a variety of data such as numerics, characters, voice, video, animation and so on, are processed concurrently in a workstation. In data processings, concurrent execution of transactions is a key to improve through-puts. However, concurrent execution without concurrency control may cause inconsistent results. Thus, the concurrency control must be introduced in such systems. However, in MMDP it is ineffective to adopt previous concurrency control methods for ordinal databases since multi-media data are huge and possess a real-time property. This paper discusses concurrency control for MMDP. We propose some new concepts for MMDP, and define a new serializability class called Permissible Serializability which provides high concurrency in MMDP compared with ordinal classes. Then, we propose a concurrency control algorithm TYPE for the Permissible Serializability, and show some simulation results.

The Manchester Dataflow Machine (MDFM) works with tasks of size equal to one single instruction. This fine granularity aims at exploring all parallelism at the instruction level. However, this project decision increases the instruction communication cost, which ends up to jam the interconnection network and reduces the system performance. One way to skirt this problem is to adopt variable size tasks instead of working with such small task size. In this paper, in order to study whether or not the usage of such variable size tasks in the MDFM architecture contributes to the improvement of the performance, some simulations by toy programs take place. In the simulation, variable size tasks are realized by packing the sequential instruction stretches into one task. To manage this packing, the Sequential Block (SB) technique is developed. The simulation of those packed and unpacked programs give an outline of advantages and disadvantages of working with variable size tasks, and how the SB technique should be implemented in the system.

This paper describes the design of the reflective concurrent object-oriented specification language RMondel. RMondel is designed for the specification and modeling of distributed systems. It allows the development of executable specifications which may be modified dynamically. Reflection in RMondel is supported by two fundamental features that are: Structural Reflection (SR) and Behavioral Reflection (BR). Reflection is the capability to monitor and modify dynamically the structure and the behavior of the system. We show how the features of the language are enhanced using specific meta-operations and meta-objects, to allow for the dynamic modification of types (classes) and instances using the same language. RMondel specification can be modified by adding or modifying types and instances to get a new adapted specification. Consistency is checked dynamically at the type level as well as at the specification level. At the type level, structural and behavioral constrations are defined to preserve the conformance of types. At the specification level, a transaction mechanism and a locking protocol are defined to ensure the consistency of the whole specification.

Complexity of Boolean functions satisfying the propagation criterion (PC), an extended notion of the perfect nonlinearity, is discussed on several computation models. The following topics are investigated: (i) relationships between the unateness and the degree of the PC, (ii) the inversion complexity of perfectly nonlinear Boolean functions, (iii) the formula size of Boolean functions that satisfy the PC of degree 1, (iv) the area-time-square complexity of VLSI circuits computing perfectly nonlinear Boolean functions, (v) the OBDD size perfectly nonlinear Boolean functions.

This paper describes a method for screening psychiatric patients based on a questionnaire consisting of simple yes/no questions regarding to physical, mental conditions and subjective symptoms which is provided at their first visit to the hospital. The analysis of the questionnaire is important to understand patients' background. One hundred filled out questionnaires were utilized for constructing and evaluating a pseude Bayesian classifier which classifies patients into three categories i.e. Schizophrenic, emotional and neurotic disorders with average correct prediction rate of 73.3%. The rate was 16.6% higher than the result given by experienced medical doctors and the method will be a useful mean for automatic screening of the psychiatric patients.

Next generation personal communication systems will provide a range of different services to moving users. In parallel, packet switching is being proposed as a way to statistical multiplexing and hence to better resource exploitation. The co-existence of different services may prove difficult due to the different requirements on quality of service parameters like packet loss, delay, and so on. This requires a careful design of Call Admission Control policies, which are to be quite different from those used in fixed network, due to two phenomena which are typical of mobile systems, namely co-channel interference and handovers. In this paper we address these complex topics, and propose some basic rules for Call Admission Control policies suitable in this context.

We extend the theorem of Gramlich on modular termination of term rewriting systems, by relaxing the disjointness condition and introducing the composability instead. More precisely, we prove that if R1, R-1 are composable, terminating term rewriting systems such that their union is nonterminating then for some a {1, -1}, Ra OR is nonterminating and R-aRa is Fa-lifting. Here, OR is defined to be the special system {or(x, y) x, or(x, y) y}, Fa is the set of function symbols associated with Ra, and an Fa-lifting system contains a rule which has either a variable or a symbol from Fa at the leftmost position of its right-hand side. The extended theorem is stronger than the original one in that it relaxed the disjointness and constructor-sharing conditions and allowed the two systems to share defined symbols in common under the restriction of composability. The corollaries of the theorem show several sufficient conditions for decomposability of termination, which are useful for proving termination of term rewriting systems defined by combination of several composable modules.

Many combinatorial problems can be efficiently solved for partial k-trees (graphs of treewidth bounded by k). The edge-coloring problem is one of the well-known combinatorial problems for which no NC algorithms have been obtained for partial k-trees. This paper gives an optimal and first NC parallel algorithm to find an edge-coloring of any given partial k-tree with bounded degrees using a minimum number of colors. In the paper k is assumed to be bounded.

We investigated performance of routing schemes in B-ISDN, for heterogeneous traffic flows under various bandwidths. In particular, we compared the simulated performance of these schemes by evaluating their blocking probabilities. To achieve high performance, these schemes use special kinds of routing algorithm, one which is pre-selection algorithm and one which is cyclic algorithm. We investigated the efficiency of the pre-selection algorithm and the robustness of the cyclic algorithm for nonuniform traffic and network resources. We found that these routing algorithm schemes can compensate for errors in resource design.

A self-induced-transparent (SIT) system that takes advantage of morphology dependent resonances (MDR's) in a Mie-sized microsphere doped with a resonant material is proposed. The present system is doubly resonant: one has microscopic origin (the two-level system), while the other has macroscopic origin (the MDR). In this geometry, owing to the feedback action of MDR's, the pulse area can be much expanded, and thus the electric-field amplitude of the incident pulse can be reduced substantially compared with the conventional one-way SIT propagation. Theoretical results that incorporate dephasing due to structural imperfections are shown.

Some CMOS gates are topologically asymmetric in inputs, even though they are logically symmetric. It implies a possibility to reduce power consumption by optimizing signal assignment to the inputs. In this study we theoretically derive power consumption of 2-input NAND gate based on transition probability of input signals, with taking into account charging current due to an internal node. We also propose a signal assignment method to input terminals for reducing power consumption reduction by extending our method for large circuits, and demonstrate the effect of power consumption reduction by the present method.

A monolithic linear power amplifier IC operating with a single low 2.7-V supply has been developed for 1.9-GHz digital mobile communication systems, such as the Japanese personal handy phone system (PHS). Refractory WNx/W self-aligned gate GaAs power MESFETs have been successfully developed for L-band power amplification, and this power amplifier operates with high efficiency and low distortion at a low voltage of 2.7 V, without any additional negative voltage supply, by virtue of small drain knee voltage, high transconductance and sufficient breakdown voltage of the power MESFET. An output power of 23.0 dBm and a high power-added efficiency of 30.8% were attained for 1.9-GHz π/4-shifted QPSK (quadrature phase shift keying) modulated input when adjacent channel leakage power level was less than -60 dBc at 600 kHz apart from 1.9 GHz.