This is an attempt to examine the contact resistance of a composite material which is used for sliding contacts. The composite material used here is sintered by dispersing the solid lubricant WS2 into the metallic base alloy Cu-Sn. A method based on Greenwood's formula is applied to determine how the calculated values are related to the contact resistance values obtained in our experiments. As a result, the composite material mated with the carbon specimen is found nearly to corresponds to the values of those calculated by the extended Greenwood's formula, whereas its value mated with the tungsten specimen does not. In short, it is concluded that the composite material mated with the carbon specimen consists of multispots.

This paper presents 1V supply voltage Bi-CMOS current mode circuits. The circuits are consist of current mirrors, current comparators and current sources. The circuits have some advantages such as high accuracy, high speed, high density and low power supply. As an application of the circuits, an analog-to-digital converter (ADC) is given. The ADC operates with small chip area and low power dissipation. The performances of the proposed circuits were confirmed by using SPICE2 simulation.

In this study we shall put forward a synergetic neural network and investigate the association dynamics. The present neuron model is substantially based on a top down formulation of the dynamic rule of an analog neural network in contrast to the conventional framework. It is proved that a complete association can be assured up to the same number of the embedded patterns as the number of neurons. In practice an association process is carried out for practical images with 256 gray scale levels and 256256 size. In addition, a searching process of the embedded patterns is also realised by means of controlling attraction parameters. Finally a stochastic model for the dynamic process is also proposed as an intermediate model between the association and the searching of the embedded patterns. Finally a stochastic property of the present model is characterized by fractal dimension of the excitation level of a neuron.

We give a tutorial on high-level synthesis of VLSI. The evolution of digital system synthesis techniques and the need for higher level design automation tools are first discussed. We then point out essential issues to the successful development and acceptance by the designers of a high-level synthesis system. Techniques that have been proposed for various subtasks of high-level synthesis are surveyed. Possible applications of the high level synthesis in area other than chip design are forecast. Finally, we point out several directions for possible future research.

Connectivity (of node-to-node) is generally used to examine the robustness of graphs. When telecommunication network switches are integrated into logical switching areas, we should examine node-to-area connectivity rather than node-to-node connectivity. In a previous paper, we proposed node-to-area (NA) connectivity using area (subset of nodes) graph. In this paper, we consider a further constraint: "there is a path that does not include other nodes in the source node area." We call this property, directly NA-connected. Application of this constraint makes telecommunications networks robust against locally striking disasters. The problem of finding the maximum number of edge deletions that still preserves the direct NA-connection is shown to be NP-hard. It was shown in our previous paper that an NA-connected spanning tree is easily found; this paper shows that the problem of finding a directly NA-connected spanning tree is also NP-hard. We propose an O(|E||X|) approximation algorithm that finds a directly NA-connected spanning subgraph with an edge nummber not exceeding 2|V|3 for any NA-connected area graph that satisfies a described simple condition. (|V|,|E|,and |X| are the numbers of nodes, edges, and areas, respectively.)

A parallel overlapping preconditioner is applied to ICCG method and the effect of the parallel preconditioning on the convergence of the method is investigated by solving large scale block tridiagonal linear systems arising from the discretization of Poisson's equation. Compared with the original ICCG method, the parallel preconditioned ICCG method can solve the problems in high parallelism with slight increasing the number of iterations. Furthermore, the speedup and the efficiency are evaluated for the parallel preconditioned ICCG method by substituting the experimental results into formulae of complexity. For example, when a domain of simulation is discretized on a 250250 rectangular grid and the preconditioner is divided into 249 smaller ones, its speedup is 146.3 with the efficiency 0.59.

We developed an eye-contact technique using a blazed half-transparent mirror (BHM), which is a micro-HM array arranged on the display surface, to make a compact eye-contact videophone. This paper describes a new BHM structure that eliminates ghosts and improves image quality. In the new BHM, the reflection and transmission areas are separated to exclude ghosts from appearing in the captured image. We evaluated the characteristics of the captured and displayed images. The results show that the contrast ratio of the captured image and the brightness of both captured and displayed images are much better than with the previous BHM.

The performance of the hybrid-ARQ scheme with a convolutional code, in which the retransmission criterion is based on an estimated decoding error rate, is evaluated for moderately time-varying channels. It is shown by computer simulations that the simple average diversity combining scheme can almost attain the same performance as the optimally weighted diversity combining scheme. For the whole and partial retransmission schemes with the average diversity combining, the theoretical bounds of throughput and bit error rate are derived, and it is shown that their bounds are tight and the treated schemes can attain a given error rate with good throughput for moderately time-varying channels. Furthermore, the throughput is shown to be improved by the partial retransmission scheme compared with the whole retransmission scheme.

Carrier mobility is one of the most fundamental parameters in semiconductor device modeling, and many mobility models have already been reported. Especially for numerical device simulators, many local models which are functions of impurity concentration and electric field at each local point have been studied. However, concerning their dependence on impurity concentration including carrier screening effects, these models suffer parameter fitting procedure because of their empirical formulation. In such models, carrier screening effects to the Coulomb potential of ionized impurity are not sufficiently considered, although we can find some models which treat the effects as only a small perturbation term. According to the simple theory of Brooks and Herring, carrier screening effects should be included in strong combination with impurity concentration terms and cannot be treated as additional perturbations. Although Brooks-Herring theory is successful, it also suffers from overestimation of the mobility values at concentration higher than 1018 cm-3 which causes some other complicated phenomena. Therefore there have been no models which directly use Brooks-Herring formula. But it is true that such screening effects should be considered when carrier concentration differs from impurity concentration as in the inversion layers of MOSFETs. We have developed a new mobility model for its dependence of impurity and carrier concentration based on the theory of Brooks-Herring. Brooks-Herring theory is based on simple physics of screened Coulomb potential, and therefore makes the model to include effects of free carriers without an artifitial formula. For high doping regime, an additional term has been introduced in Brooks-Herring formula to correct the high doping effects. Except for this term, the model should be most appropriate for including the carrier screening effects upto the concentration of 1018 cm-3. The new model is implimented in a device simulator, and is applied to the evaluation of MOSFETs especially for the universal curves of inversion layer mobility. Moreoever, the applications to the depletion-type MOSFET confirm the validity of the screening effects. The purpose of this paper is to propose the new mobility model and to show its validity through these applications to MOSFETs.

The Double-Sided Rugged poly Si (DSR) technology has been developed for high density DRAMs. The DSR technology was achieved using transformation of rugged poly Si caused by ion implantation. The DSR can increase the surface area of the storage electrode, because it has rugged surfaces on both upper and lower sides. The 2-FINs STC (STacked Capacitor cell) with DSR was fabricated in the cell size of 0.72 µm2, and it is confirmed that the DSR can increase the surface area 1.8 times larger than that of smooth poly Si. It is expected that 25 fF/bit is obtained with a 300 nm-thick storage electrode. These effects show that sufficient capacitance for 256 Mb DRAMs is obtained with a low storage electrode. It is confirmed that there is no degradation in C-V and I-V characteristics. Moreover, the DSR needs neither complicated process steps nor special technologies. Therefore, the DSR technology is one of the most suitable methods for 256 Mb DRAMs and beyond.

The optical characteristics of the fiber loop polarizer are investigated considering the birefringence in the fiber loop. The experimental and the theoretical spectrum transmissions agree well with each other. The extinction ratio and the insertion loss of the fiber polarizers have been improved for practical use.

We propose a method for configuring LSI manufacturing lines so that they can not only be used to manufacture low-cost LSIs in bulk quantities but also can be used to manufacture small lots with ultra-short TAT. This is achieved by adding a relatively small amount of single-wafer processing equipment to a existing conventional processing line, and therefore involves minimum investment.

This paper discusses a CMOS differential-difference amplifier circuit suitable for low voltage operation. A new multiple weighted input transconductor circuit structure is suggested to be use in DDA implementation. The proposed DDA can be employed in several analog/digital systems to improve their parameters. Selected examples of the proposed transconductor/DDA applications are also discussed.

The design procedure of a multithreaded processor dedicated to the image generation is described, which can be achieved by means of a high-level synthesis tool PARTHENON. The processor employs a multithreaded architecture which is a novel promising approach to the parallel image generation. This paper puts special stress on the high-level synthesis scheme which can simplify the behavioral description for the structure and control of a complex hardware, and therefore enables the design of a complicated mechanism for a multithreaded processor. Implementation results of the synthesis are also shown to demonstrate the performance of the designed processor. This processor greatly improves the throughput of the image generation so far attained by the conventional approach.

This paper deals with network performance of 64kbit/s-based services supported in an ATM network and an ATM interworking network with 64kbit/s-based networks. It first clarifies network performance issues giving a model and objectives of study and experiment. A result of computational analysis is then presented, where a cell loss ratio of an order of 10-4 or 10-5 is obtained to give a performance equivalent to that currently used as objective values in existing networks for a 64kbit/s digital level. In order to capture the impact of cell loss and associated performance for application levels, an experimental test has been carried out using typical applications. Test results show that the cell loss ratio needs to be approximately ten times better than the bit error ratio for comparable performance for application levels. A cell loss ratio of better than 10-5, or an order of 10-6 considering an interworking situation, seems to be necessary according to the test results. It is further clarified by the test that a single cell is more valuable than a multiplexed cell for providing better cell loss resilience characteristics. Although not all applications of 64kbit/s networks have been tested, it is expected that the test results can be used as guidance for considering the support of 64 kbit/s services in an ATM and interworking networks.

A scalable and flexible ASIC CIM system distributed on UNIX workstations, ORCHARD , has been developed. It is designed from three viewpoints: (1) cost and TAT reduction in system construction, (2) flexibility in data management for quality control, and (3) precise and quick scheduling and effective lot tracking to control TAT for each lot. The concept of a "virtual machine" is introduced to connect equipment having various protocols to a host system. The virtual machine is automatically generated at an average automatic generation ratio of as high as 89%, which leads to a reduction in cost and TAT in system construction. Data for quality control is managed by changing flexibly the "data processing recipe." This recipe defines screen format, data collected from equipment, and data transfered from various databases. Precise scheduling of lots with various levels of priority is achieved by introducing a priority evaluation function, thereby reducing scheduling time to 1/20 that for manual scheduling.

We discuss properties of acyclic graph evolution driven by node-firing. The research background and basic concepts of acyclic graph evolution are from the mutual exclusion problem in distributed environments. We proposed in our previous work a mutual exclusion protocol which is based on the notion of evolution trajectories of acyclic graphs. In this paper, we analyze firing concurrency and periodicity of the acyclic graph evolution, from graph theoretical point of views, and investigate topological conditions for assuring the number of firable nodes below a some fixed constant, at any instance of the evolution trajectory. A marked graph, a subclass of Petri nets, is often utilized as a proof tool in analysis.

An on-line scheduler for ASIC manufacturing line management has been developed. The parameters in the schedule models and the dynamic priority curve in the schedule algorithm were adjusted to obtain schedules well-suited to practical ASIC line management and control. The scheduler is connected to the user interface control module of our ASIC CIM system. In order to facilitate on-line scheduling, we clarify the performance requirements of the computer used for the scheduler with respect to the line scale. Using a current EWS, the scheduler can easily make a one-day schedule for a small-scale line with an annual throughput of less than 1,000 lots within 10 minutes. To cope with larger-scale lines, the multiple scheduling method allows schedules to be produced quickly and efficiently. Therefore, the scheduler can respond flexibly to changes in production plan and line resources and the control delivery date of each lot.

The discrete-time short-time Fourier transform (STFT) is known as a useful tool for analyzing and synthesizing signals. This paper introduces an extention of the well-known STFT to a general form which is more suitable for high resolutional signal analysis. A channel frequency division scheme is developed for realizing arbitrary bandwidth and center frequency so as to improve resolution performance. It is based on a nonuniform filter bank structure with integer decimation and interpolation factors. A design example of the generalized STFT using symmetric windows is given.

In this paper we propose a co-design method for control systems using combination of models. By co-design," we mean a cooperative design method in which the behavior of the entire system is simulated as a single model while parameters of the system are being optimized. Our co-design method enables the various subsystems in the system, which have been designed independently as tasks assigned to different designers in the traditional design method, to be designed simultaneously in a unified cooperative way from the system-wide perspective of a system designer. Our proposed method combines models of controlling and controlled subsystems into a single model for the behavior of the entire control system. After the optimum control conditions are determined through simulation of the combined models, based on the corresponding algorithms and parameters, ASIC design proceeds quickly with accurate verification using iterative replacements of the behavior model by the electronic circuit model. To evaluate the proposed method, we implemented a design environment. We then applied our method to the design of ASICs in three test cases (in a control system and in audio-visual systems) to investigate its effectiveness. This paper introduces the concepts of the proposed co-design method, the design environment and the experimental results, and points out the new issues for system design.