Circuit design techniques for linearizing adaptively biased differential pairs are described. An emitter-and source-coupled pair is adaptively biased by a squaring circuit to linearize its transconductance, one of whose inputs is divided by resistors. An input signal for a differential pair or a squaring circuit is set to an adequate amplitude by a resistive divider without sacrificing linearity. Therefore, a differential pair is biased by the output current of a squaring circuit and they are coupled directly. There are three design techniques for squaring circuits. One is the transistor-size unbalance technique. Another is the bias offset technique. A third is the multitail technique. The bipolar and MOS squaring circuits discussed in this paper were proposed by the author previously, and consist of transistor-pairs with different transistor size (i.e., the emitter areas or gate W/L values are different), transistor-pairs with the same bias offset, or a multitail cell(i.e., a triple-tail cell or quadritail cell). Several kinds of squaring circuits consisting of such transistor-pairs are applied to produce the quadratic bias currents for compensating the nonlinearity of an emitter-and source-coupled pair. Therefore, four circuits using emitter-coupled pairs with adaptive-biasing current and four circuits using source-coupled pairs with adaptive-biasing current are proposed and analyzed in depth. Furthermore, a circuit configuration for low voltage operation is also introduced and verified with bipolar transistor-arrays on a breadboard.

In the actual sound environmental systems, it seems to be essentially difficult to exactly evaluate a whole probability distribution form of its response fluctuation, owing to various types of natural, social and human factors. We have reported a unified probability density expression in the standard expansion form of Hermite type orthonormal series taking a well-known Gaussian probability density function (abbr. p.d.f.) as the basis for generally evaluating non-Gaussian, non-linear correlation and/or non-stationary properties of the fluctuation phenomenon. However, in the real sound environment, there still remain many actual problems on the necessity of improving the above standard type probability expression for practical use. First, a central point in this paper is focused on how to find a new probabilistic theory of practically evaluating the variety and complexity of the actual random fluctuations, especially through newly introducing an equvivalence transformation toward the standard type probability expression mentioned above in the expansion form of Hermite type orthonormal series. Then, the effectiveness of the proposed theory has been confirmed experimentally too by applying it to the actual problems on the response probability evaluation of various sound insulation systems in an acoustic room.

We report the first monolithic integration of InGaAs/InAlAs resonant tunneling diode (RTD) and high electron mobility transistor (HEMT) epitaxially grown on an InP substrate. The transconductance for a 1-µm gate HEMT was 430 mS/mm and the peak-to-valley current ratio of the RTD was 5.1. Using the integrated structure, we demonstrate basic digital circuits to show low power characteristics of an RTD-load inverter and a static RAM cell circuit, consisting of a single transistor with two RTDs on the transistor. The memory cell circuit exhibits bistability, based on the RTD's negative differential resistance (NDR), at supply voltages from 0.6 to 1.1 V. The static power consumption was 7.3 µW/gate for the inverter and 3.0 µW for memory cell.

In this letter we propose a stabilizing method of phase control for resistively coupled oscillator networks. To demonstrate the effect of the control, we consider the coupled oscillator system containing only voltage type of connections. A state feedback technique to resistor sub-network is used to control the phase of synchronized oscillation. The technique is applied to two and three coupled oscillator cases. Finally we present experimental results, which agree well with the theory.

A method for painting a sequence of monochromatic images is proposed. In this method, a color model, whose base components are hue, saturation and intensity, is used to keep the lightness of images unchanged before and after painting. Two successive frames in the monochromatic image sequence and a colored image of the first frame which is interactively painted, are analyzed in order to paint the next monochromatic frame. The painting process is composed of two phases, that is, an automatic coloring phase and an interactive retouching phase. In the automatic coloring phase, hierarchical image segmentation and region matching procedures are performed, and the two attributes of hue and saturation are mapped from the painted image of the first frame to the next image. In the retouching phase, using an interactive paint system based on the color model, users can modify the chromatic components of pixels whose colors were not mapped correctly. Several experiments show that our method is very effective in reducing tedious painting.

With the development in portable electronic equipment, the demand for secondary batteries of high energy density is increasing. Recently, nickel metal hydride secondary batteries (Ni/MH) are expanding the market, and lithium ion secondary batteries have been newly developed and commercialized. This paper describes in detail Ni/MH and lithium ion secondary batteries, and reports on their development state and characteristics.

Many combinatorial problems can be efficiently solved for partial k-trees (graphs of treewidth bounded by k). The edge-coloring problem is one of the well-known combinatorial problems for which no NC algorithms have been obtained for partial k-trees. This paper gives an optimal and first NC parallel algorithm to find an edge-coloring of any given partial k-tree with bounded degrees using a minimum number of colors. In the paper k is assumed to be bounded.

We extend the theorem of Gramlich on modular termination of term rewriting systems, by relaxing the disjointness condition and introducing the composability instead. More precisely, we prove that if R1, R-1 are composable, terminating term rewriting systems such that their union is nonterminating then for some a {1, -1}, Ra OR is nonterminating and R-aRa is Fa-lifting. Here, OR is defined to be the special system {or(x, y) x, or(x, y) y}, Fa is the set of function symbols associated with Ra, and an Fa-lifting system contains a rule which has either a variable or a symbol from Fa at the leftmost position of its right-hand side. The extended theorem is stronger than the original one in that it relaxed the disjointness and constructor-sharing conditions and allowed the two systems to share defined symbols in common under the restriction of composability. The corollaries of the theorem show several sufficient conditions for decomposability of termination, which are useful for proving termination of term rewriting systems defined by combination of several composable modules.

We investigated performance of routing schemes in B-ISDN, for heterogeneous traffic flows under various bandwidths. In particular, we compared the simulated performance of these schemes by evaluating their blocking probabilities. To achieve high performance, these schemes use special kinds of routing algorithm, one which is pre-selection algorithm and one which is cyclic algorithm. We investigated the efficiency of the pre-selection algorithm and the robustness of the cyclic algorithm for nonuniform traffic and network resources. We found that these routing algorithm schemes can compensate for errors in resource design.

Two types of dynamic termination, latch-type and RC-type, are useful for low-power high-speed chip interconnection where the transmission line is terminated only if the signal is changed. The gate of the termination MOS in the latch-type is driven by a feedback inverter, and that in the RC-type is driven by a differentiating signal through the resistor and capacitor. The power dissipation is 13% for the latch-type, and 11% for the RC-type in a DC termination scheme, and the overshoot is 32% for the latch-type, and 16% for the RC-type in an open scheme, both at a signal amplitude of 2 V. The RC-type is superior for signal swing as low as a 1 V. On the other hand, RC termination requires large capacitance, and thus high power. Diode termination is not effective for a small swing because of the large ON voltage of diodes.

An on-line scheduler for ASIC manufacturing line management has been developed. The parameters in the schedule models and the dynamic priority curve in the schedule algorithm were adjusted to obtain schedules well-suited to practical ASIC line management and control. The scheduler is connected to the user interface control module of our ASIC CIM system. In order to facilitate on-line scheduling, we clarify the performance requirements of the computer used for the scheduler with respect to the line scale. Using a current EWS, the scheduler can easily make a one-day schedule for a small-scale line with an annual throughput of less than 1,000 lots within 10 minutes. To cope with larger-scale lines, the multiple scheduling method allows schedules to be produced quickly and efficiently. Therefore, the scheduler can respond flexibly to changes in production plan and line resources and the control delivery date of each lot.

The performance of a nonblocking switch with two kinds of correlated input calls is analyzed. We define two kinds of calls as the waiting call and the immediate call, and assume that the immediate call has the priority over the waiting call. If the traffic density of one kind of calls is larger than maximum throughput, the ratio of the corresponding kind of calls to the total traffic must be restrained in some range. We derive the maximum ratio of the waiting call by using two approximate methods. The effects of traffic densities and transition probabilities of two kinds of calls on the maximum ratio of the waiting call are also considered. It is shown that, if the traffic density of the immediate call is smaller than that of the waiting call, our approximate methods are useful to derive the maximum ratio of the waiting call to the total traffic.

This paper proposes a universal structure for STM-N(N=1, 2, 3, ) multiplex line terminals that only utilizes N chips CMOS LSIs for Section OverHead (SOH) processing. The uniquely configured LSIs are applicable to any STM-N line terminal equipment. Reasonable frame alignment performance attributes, such as the maximum average reframe time, false in-frame time, out-of-frame detection time, and misframe time, are calculated for the configuration. A prototype SOH processing LSI built on 0.8m BiCMOS technology successfully realizes the functions needed for multiplex section termination. The STM-64 frame is also demonstrated using the proposed circuit configuration and prototype LSIs.

Carrier mobility is one of the most fundamental parameters in semiconductor device modeling, and many mobility models have already been reported. Especially for numerical device simulators, many local models which are functions of impurity concentration and electric field at each local point have been studied. However, concerning their dependence on impurity concentration including carrier screening effects, these models suffer parameter fitting procedure because of their empirical formulation. In such models, carrier screening effects to the Coulomb potential of ionized impurity are not sufficiently considered, although we can find some models which treat the effects as only a small perturbation term. According to the simple theory of Brooks and Herring, carrier screening effects should be included in strong combination with impurity concentration terms and cannot be treated as additional perturbations. Although Brooks-Herring theory is successful, it also suffers from overestimation of the mobility values at concentration higher than 1018 cm-3 which causes some other complicated phenomena. Therefore there have been no models which directly use Brooks-Herring formula. But it is true that such screening effects should be considered when carrier concentration differs from impurity concentration as in the inversion layers of MOSFETs. We have developed a new mobility model for its dependence of impurity and carrier concentration based on the theory of Brooks-Herring. Brooks-Herring theory is based on simple physics of screened Coulomb potential, and therefore makes the model to include effects of free carriers without an artifitial formula. For high doping regime, an additional term has been introduced in Brooks-Herring formula to correct the high doping effects. Except for this term, the model should be most appropriate for including the carrier screening effects upto the concentration of 1018 cm-3. The new model is implimented in a device simulator, and is applied to the evaluation of MOSFETs especially for the universal curves of inversion layer mobility. Moreoever, the applications to the depletion-type MOSFET confirm the validity of the screening effects. The purpose of this paper is to propose the new mobility model and to show its validity through these applications to MOSFETs.

The optical characteristics of the fiber loop polarizer are investigated considering the birefringence in the fiber loop. The experimental and the theoretical spectrum transmissions agree well with each other. The extinction ratio and the insertion loss of the fiber polarizers have been improved for practical use.

Surface-channel PMOSFETs are suitable for use in the quarter micron CMOS devices. For surface-channel PMOSFETs with p+ poly-Si gates, boron penetration and hot-carrier effects were investigated. When the annealing temperature is higher and the gate oxide is thinner, a larger threshold voltage shift was observed for p+ poly-Si PMOSFETs, because of boron penetration. Furthermore, PMOSFETs with BF2-implanted gates cause larger boron penetration than those with Boron-implanted gates. Howerer, the PMOSFET lifetime, determined by hot-carrier reliability, does not depend on the degree of boron penetration. Instead, it depends on doping species, that is, BF2 and Boron. PMOSFETs with BF2-implanted gates have about 100 times longer lifetime than those with Boron-implanted gates. The main reason for the longer lifetime of BF2-doped PMOSFETs is the incorporation of fluorine in the gate oxide of the PMOSFET with the BF2-implanted gate, resulting in the smaller electron trapping in the gate oxide. The maximun allowed supply voltage,based on the hot-carrier reliability, is higher than4V for sub-half micron PMOSFETs with BF2- or Boron-implanted poly Si gates.

Degradation of metal-oxide-semiconductor field-effect transistors (MOSFETs) reliability such as the relative transconductance reduction by plasma exposure is evaluated. The linear region peak transconductance (gm) decreases with antenna ratio (exposed antenna area/gate area) due to the plasma-induced Si-SiO2 interface state generation. The Si-SiO2 interface-related gm reduction which is defined as (gm0gm)/gm, where gm0 is the initial value of gm, decreases as the gate oxide thickness decreases. It is also found that the decreasing amount of gm depends on the conduction current from the plasma. The correlation between the (gm0gm)/gm and the plasma-induced reduction of charge-to-breakdown of the gate oxide with a constant current stress (ΔQBD) is observed, and the result shows that the gm reduction of nMOSFET during the plasma process is severe to the plasma-induced damage compared with the gate oxide breakdown.

The Double-Sided Rugged poly Si (DSR) technology has been developed for high density DRAMs. The DSR technology was achieved using transformation of rugged poly Si caused by ion implantation. The DSR can increase the surface area of the storage electrode, because it has rugged surfaces on both upper and lower sides. The 2-FINs STC (STacked Capacitor cell) with DSR was fabricated in the cell size of 0.72 µm2, and it is confirmed that the DSR can increase the surface area 1.8 times larger than that of smooth poly Si. It is expected that 25 fF/bit is obtained with a 300 nm-thick storage electrode. These effects show that sufficient capacitance for 256 Mb DRAMs is obtained with a low storage electrode. It is confirmed that there is no degradation in C-V and I-V characteristics. Moreover, the DSR needs neither complicated process steps nor special technologies. Therefore, the DSR technology is one of the most suitable methods for 256 Mb DRAMs and beyond.

The performance of the hybrid-ARQ scheme with a convolutional code, in which the retransmission criterion is based on an estimated decoding error rate, is evaluated for moderately time-varying channels. It is shown by computer simulations that the simple average diversity combining scheme can almost attain the same performance as the optimally weighted diversity combining scheme. For the whole and partial retransmission schemes with the average diversity combining, the theoretical bounds of throughput and bit error rate are derived, and it is shown that their bounds are tight and the treated schemes can attain a given error rate with good throughput for moderately time-varying channels. Furthermore, the throughput is shown to be improved by the partial retransmission scheme compared with the whole retransmission scheme.

0.15 µm CMOS transistors have been fabricated. TiSi2 salicide was used for the gate electrode and source/drain to reduce parasitic resistance. Electron beam (EB) lithography was used for the gate patterning. Since the channel impurity was implanted only around the gate to reduce the junction capacitance, a reasonably short ring oscillator delay of 33 ps was obtained at 1.9 V supply voltage. The parasitic resistance and capacitance contribution on the delay time was analyzed by SPICE simulation. It was shown that the localized channel implant is effective for scaling the delay time and power consumption, because the source/drain size difficult to scale down to as small as the gate length.