A flexible and low-cost menagement technology is desired for fabrication line of both ASICs and cutting edge LSIs. To meet such desire, a management technology named "super operator shifts" has been proposed. After taking operator's skill level into consideration, an ASIC line manager can stretch line working time by use of the super operator shifts. It results that he can successfully get 3-shifts turn around time for severe-delivery-date lots with a payment equal to about 2-shifts line-cost.

The paper describes a new algorithm for Boolean matching, which is based on BDD structure manipulation. Pruning of the search space takes place after partial assignments if certain subgraphs of two BDD's become inequivalent. This pruning is different from existing techniques, so that the search space is further reduced. Another feature of this algorithm is topological filtering. Usually, many functions have no matchings and this is easily found by only counting the number of minterms. To check it quickly, upper and lower bounds of minterm count are calculated from topological information. Using these bounds, functions that have no matchings are discarded without building their BDD's.

This paper describes an exact symbolic formulation of resource-constrained scheduling which allows speculative operation execution in arbitrary forward-branching control/data paths. The technique provides a closed-form solution set in which all satisfying schedules are encapsulated in a compressed OBDD-based representation. An iterative construction method is presented along with benchmark results. The experiments demonstrate the ability of the proposed technique to efficiently extract parallelism not explicitly specified in the input description.

In order to shorten the time-to-market, Application-Specific Integrated Circuits (ASIC's) are designed from a library of pre-defined layout implementations for register-transfer modules such as multipliers, adders, RAM, ROM, etc. Current approaches to selecting the implementations from the library usually deal with their timing-area estimates and do not consider delay of the intermodule wiring. However, as sub-micron design rules are utilized for IC fabrication, wiring delay becomes comparable to the functional unit delay and can not longer be ignored even in register-transfer synthesis. In this paper we propose an algorithm that combines module selection with Performance-Driven module placement and reduces an impact of wiring on sub-micron ASIC performance. The algorithm not only efficiently exploits multiple module realizations in the design library, but also finds the module placement which minimizes wiring delay. Experimental results on several benchmarks show that considering both module and wiring issues, more than 30% reduction of the total circuit delay can be achieved.

In this paper, we demonstrate how Yamakawa's chaotic chips and Chua's circuits can be used to implement a secure communication system. Furthermore, their performance for the secure communication is discussed.

The design procedure of a multithreaded processor dedicated to the image generation is described, which can be achieved by means of a high-level synthesis tool PARTHENON. The processor employs a multithreaded architecture which is a novel promising approach to the parallel image generation. This paper puts special stress on the high-level synthesis scheme which can simplify the behavioral description for the structure and control of a complex hardware, and therefore enables the design of a complicated mechanism for a multithreaded processor. Implementation results of the synthesis are also shown to demonstrate the performance of the designed processor. This processor greatly improves the throughput of the image generation so far attained by the conventional approach.

We propose an asymmetric neural network which can solve inequality-constrained combinatorial optimization problems that are difficult to solve using symmetric neural networks. In this article, a knapsack problem that is one of such the problem is solved using the proposed network. Additionally, we study condition for obtaining a valid solution. In computer simulations, we show that the condition is correct and that the proposed network produces better solutions than the simple greedy algorithm.

In this paper, we propose a hybrid hierarchical global router for multi-layer VLSI's, which executes routing and layering simultaneously. This novel approach, a hybrid hierarchical global router, is a combination of a topdown and a bottomup hierarchical routers, and may be one of interesting routing techniques. We also show experimental results, which demonstrate the superiority of the hybrid hierarchical approach. This approach may have many possibilities to be used in a various fields.

Carrier mobility is one of the most fundamental parameters in semiconductor device modeling, and many mobility models have already been reported. Especially for numerical device simulators, many local models which are functions of impurity concentration and electric field at each local point have been studied. However, concerning their dependence on impurity concentration including carrier screening effects, these models suffer parameter fitting procedure because of their empirical formulation. In such models, carrier screening effects to the Coulomb potential of ionized impurity are not sufficiently considered, although we can find some models which treat the effects as only a small perturbation term. According to the simple theory of Brooks and Herring, carrier screening effects should be included in strong combination with impurity concentration terms and cannot be treated as additional perturbations. Although Brooks-Herring theory is successful, it also suffers from overestimation of the mobility values at concentration higher than 1018 cm-3 which causes some other complicated phenomena. Therefore there have been no models which directly use Brooks-Herring formula. But it is true that such screening effects should be considered when carrier concentration differs from impurity concentration as in the inversion layers of MOSFETs. We have developed a new mobility model for its dependence of impurity and carrier concentration based on the theory of Brooks-Herring. Brooks-Herring theory is based on simple physics of screened Coulomb potential, and therefore makes the model to include effects of free carriers without an artifitial formula. For high doping regime, an additional term has been introduced in Brooks-Herring formula to correct the high doping effects. Except for this term, the model should be most appropriate for including the carrier screening effects upto the concentration of 1018 cm-3. The new model is implimented in a device simulator, and is applied to the evaluation of MOSFETs especially for the universal curves of inversion layer mobility. Moreoever, the applications to the depletion-type MOSFET confirm the validity of the screening effects. The purpose of this paper is to propose the new mobility model and to show its validity through these applications to MOSFETs.

The optical characteristics of the fiber loop polarizer are investigated considering the birefringence in the fiber loop. The experimental and the theoretical spectrum transmissions agree well with each other. The extinction ratio and the insertion loss of the fiber polarizers have been improved for practical use.

Surface-channel PMOSFETs are suitable for use in the quarter micron CMOS devices. For surface-channel PMOSFETs with p+ poly-Si gates, boron penetration and hot-carrier effects were investigated. When the annealing temperature is higher and the gate oxide is thinner, a larger threshold voltage shift was observed for p+ poly-Si PMOSFETs, because of boron penetration. Furthermore, PMOSFETs with BF2-implanted gates cause larger boron penetration than those with Boron-implanted gates. Howerer, the PMOSFET lifetime, determined by hot-carrier reliability, does not depend on the degree of boron penetration. Instead, it depends on doping species, that is, BF2 and Boron. PMOSFETs with BF2-implanted gates have about 100 times longer lifetime than those with Boron-implanted gates. The main reason for the longer lifetime of BF2-doped PMOSFETs is the incorporation of fluorine in the gate oxide of the PMOSFET with the BF2-implanted gate, resulting in the smaller electron trapping in the gate oxide. The maximun allowed supply voltage,based on the hot-carrier reliability, is higher than4V for sub-half micron PMOSFETs with BF2- or Boron-implanted poly Si gates.

Degradation of metal-oxide-semiconductor field-effect transistors (MOSFETs) reliability such as the relative transconductance reduction by plasma exposure is evaluated. The linear region peak transconductance (gm) decreases with antenna ratio (exposed antenna area/gate area) due to the plasma-induced Si-SiO2 interface state generation. The Si-SiO2 interface-related gm reduction which is defined as (gm0gm)/gm, where gm0 is the initial value of gm, decreases as the gate oxide thickness decreases. It is also found that the decreasing amount of gm depends on the conduction current from the plasma. The correlation between the (gm0gm)/gm and the plasma-induced reduction of charge-to-breakdown of the gate oxide with a constant current stress (ΔQBD) is observed, and the result shows that the gm reduction of nMOSFET during the plasma process is severe to the plasma-induced damage compared with the gate oxide breakdown.

The Double-Sided Rugged poly Si (DSR) technology has been developed for high density DRAMs. The DSR technology was achieved using transformation of rugged poly Si caused by ion implantation. The DSR can increase the surface area of the storage electrode, because it has rugged surfaces on both upper and lower sides. The 2-FINs STC (STacked Capacitor cell) with DSR was fabricated in the cell size of 0.72 µm2, and it is confirmed that the DSR can increase the surface area 1.8 times larger than that of smooth poly Si. It is expected that 25 fF/bit is obtained with a 300 nm-thick storage electrode. These effects show that sufficient capacitance for 256 Mb DRAMs is obtained with a low storage electrode. It is confirmed that there is no degradation in C-V and I-V characteristics. Moreover, the DSR needs neither complicated process steps nor special technologies. Therefore, the DSR technology is one of the most suitable methods for 256 Mb DRAMs and beyond.

We have done a computer search for solutions of the equation x3y3z3n in the range max (|x|, |y|, |z|) 3414387 and 0 n 1000. We have discovered 21 new integer solutions for n {39, 143, 180, 231, 312, 321, 367, 439, 462, 516, 542, 556, 660, 663, 754, 777, 870}. As a result, there are 52 values of n (except n 4 (mod9)) for which no solutions are found.

A Radial Line Slot Antenna (RLSA) is a planar antenna for DBS reception. It is a kind of slotted waveguide arrays. The conductor loss is so small that high efficiency is expected irrespective of the aperture diameter. On the other hand, since a RLSA utilizes the traveling waves, the frequency bandwidth is limited by the long line effect, particularly for a larger antenna. A new Wide-Band RLSA (WB-RLSA) is proposed which halves the waveguide length and widens the frequency bandwidth. This paper presents the design and experimental results of a model antenna. A gain of 33.7dBi is measured at the edge of 800MHz bandwidth and its high potential is demonstrated.

It has become more important to reduce the protocol implementation costs as the functions of protocols have become more abundant. The protocol implementation tools which automatically generate a protocol program from a specification described by an FDT (Formal Description Technique) are very promising. Selecting SDL as a target FDT, we have developed an SDL-based protocol implementation tool which consists of a process scheduler and a compiler. Since the efficient SDL process execution is a key to generating the high-speed program, the scheduler is introduced. It provides the mechanism which executes SDL processes concurrently as light-weight-processes. It optimizes so that as few context switches take places as possible. The compiler converts as many kinds of SDL functions whose behaviors can be determined at compile time into programming language statements as possible. These elaborations are so successful that the tool can generate an efficient program. The OSI Transport protocol class 0 program generated by the compiler can process more than 500 packets per second on a 6MIPS workstation.

Circuit access control is a traffic control technique of rejecting calls arriving at a group of specified circuits to make the group free at a target scheduled time so that the capacity may be dynamically reallocated to serve other traffic demand. This technique plays an important role for resource allocation control in state-of-the-art capacity reconfigurable networks as well as for switching calls on a reserved basis in the ISDNs. In this paper, we present a novel adaptive scheme for circuit access control in order to overcome the inefficiency of the conventional deterministic scheme. The presented scheme is based only on knowledge about service time and bandwidth characteristics of calls. The transitional behavior of the circuit group under the scheme is analyzed, and the gain in utilization achieved by the adaptive scheme is examined. We treat a model of the circuit group shared by multi-slot calls with different service times, and describe the results of the transient analysis and the approximation method for evaluating the gains.

The discrete-time short-time Fourier transform (STFT) is known as a useful tool for analyzing and synthesizing signals. This paper introduces an extention of the well-known STFT to a general form which is more suitable for high resolutional signal analysis. A channel frequency division scheme is developed for realizing arbitrary bandwidth and center frequency so as to improve resolution performance. It is based on a nonuniform filter bank structure with integer decimation and interpolation factors. A design example of the generalized STFT using symmetric windows is given.

We model a road network as a directed graph G(V,E) with a source s and a sink t, where each edge e has a positive length l(e) and each vertex v has a distribution function αv with respect to the traffic entering and leaving v. This paper proposes a polynomial time algorithm for evaluating the importance of each edge e E whicn is defined to be the traffic f(e) passing through e in order to assign the required traffic Fst(0) from s to t along only shortest s-t paths in accordance with the distribution function αv at each vertex v.