In the modern hospital, the physical or chemical therapeutic procedure is regarded as paramount and psychological or spiritual care is quite frequently put aside. The goal of the Hyper Hospital" is to correct this. The Hyper Hospital is constructed in the computer based electronic network using an alternate reality system, such as the virtual reality system, as the human-machine-human interface. The nodes of the Hyper Hospital belong to a patient and also to a variety of medical care facilities; for example, the out patient office, the nursing care center, the medical examination unit, the operating theater, etc. The Hyper Hospital space consists of various kind of spaces including the alternate reality space owned and exclusively controlled by the patient himself or herself, and even the real space as well. Most of the physical contact, such as the visit to the out patient office by the patient, is actualized by the electronic connection of the patient private space and the public space of the hospital system. Prescription drugs, special care, and even the admission to the ward will be integrated into the distributed electronic network. To realize such a system, we need to solve many problems, such as the research on the network oriented architecture of the alternate reality, the development of human-machine interface particularly fitted to various disabilites, the study of the behavior of normal and diseased people, etc. The concept of the Hyper Hospital we are proposing is believed to be a new paradigm of the next generation of medical care.

We have developed a Virtual Playground," which allows various activities such as virtual playground and virtual visiting areas for hospitalized children who can not usually go outside. A Virtual Playground system is composed of TV monitors, joysticks, cameras, video transmission devices, and a graphics workstation. In a Virtual Playground environment, children can experience what is impossible or difficult during their stay in a hospital. We have completed a couple of experiments already and discussed its effects.* In our recent work, we also introduced a simple version of the Cave display to the Virtual Playground system.

The Hyper Hospital" is a novel medical care system which will be constructed on an electronic information network. The human interface of the Hyper Hospital based on the modern virtual reality technology is expected to enhance patients' ability to heal by providing computer-supported on-line visual consultations. In order to investigate the effects and features of on-line visual consultations in the Hyper Hospital, we conducted an experiment to clarify the influence of electronic interviews on the talking behavior of interviewees in the context of simulated doctor-patient interactions. Four types of distant-confrontation interviews were made with voluntary subjects and their verbal and non-verbal responses were analyzed from the behavioral point of view. The types of interviews included three types of electronic media-mediated interviews and one of a live face to face interview. There was a tendency in the media-mediated interviews that both the latency and the duration of interviewees' utterances in answering questions increased when they were compared with those of live face to face interviews. These results suggest that the interviewee became more verbose or talkative in the media-mediated interviews than in the live interviews. However, the interviewee's psychological tension was generally augmented in the media-mediated interviews, which was suggested by the delay of the initiation of conversations as compared to the conventional face-to-face interviews. We also discuss the applicability of media-mediated interviews by an electronic doctor which we are studying as a functional unit of our Hyper Hospital, a network based virtual reality space for medical care.

This paper presents a fast and practical routing algorithm implemented on a supercomputer. In previously reported work, routing has been accelerated by executing the maze algorithm on parallel processing elements. However, although many parallel algorithms and special architectures have been introduced, practical aspects have not been addressed. We therefore present a novel approach that uses a vector processor as a routing accelerator and a wavefront control algorithm in order to avoid the wasteful searches that often occur in industrial routing problems. Experimental results that show the performance of a supercomputer using these algorithms is equivalent to over 1800 VAXMIPS, the fastest yet reported for routing accelerators. Results with industrial data also prove the validity of our approach.

Processing elements (PEs) with a dynamically reconfigurable pipeline architecture allow the high-speed calculation of widely used neural model which is multi-layer perceptrons with the backpropagation (BP) learning rule. Its architecture that was proposed for a single chip is extended to multiprocessors' structure. Each PE holds an element of the synaptic weight matrix and the input vector. Multi-local buses, a swapping mechanism of the weight matrix and the input vector, and transfer commands between processor elements allow the implementation of neural networks larger than the physical PE array. Estimated peak performance by the measurement of single processor element is 21.2 MCPS in the evaluation phase and 8.0 MCUPS during the learning phase at a clock frequency of 50 MHz. In the model, multi-layer perceptrons with 768 neurons and 131072 synapses are trained by a BP learning rule. It corresponds to 1357 MCPS and 512 MCUPS with 64 processor elements and 32 neurons in each PE.

Mixed-signal LSIs promise to permit increased levels of integration, not only in voiceband but also in multi-GHz-band applications such as wireless communications and optical data links. This paper reviews the evolution of mixed-signal communications LSIs and discusses some of their design problems, including device noise and crosstalk noise. In the low-power and low-voltage designs emerging as new disciplines, the target supply voltage for voiceband LSIs is around 1 V, and even GHz-band circuits are approaching 2 V. MOS devices are expected to play an important role even in the frequency range over 100 MHz, in the area of wireless or optical communications circuits.

Development of low power MUSE (Multiple Sub-Nyquist Sampling Encoding) chip set through reduction in operating voltage (from 5 V to 3.7 V) is described. This leads to great cost reduction since the chips could be mounted on low cost plastic packages and the necessity for cooling fans to dissipate heat was obviated. To maintain compatibility with standard 5 V analog and digital peripherals such as 4 Mbit DRAMs and an A/D converter, a special voltage-level converter was also developed.

Considering the trend towards adopting high efficiency picture coding schemes into digital broadcasting services, we investigate objective picture quality scales for evaluating digitally encoded still and moving pictures. First, the study on the objective picture quality scale for high definition still pictures coded by the JPEG scheme is summarized. This scale is derived from consideration of the following distortion factors; 1) weighted noise by the spatial frequency characteristics and masking effects of human vision, 2) block distortion, and 3) mosquito noise. Next, an objective picture quality scale for motion pictures of standard television coded by the hybrid DCT scheme is studied. In addition to the above distortion factors, the temporal frequency characteristics of vision are also considered. Furthermore, considering that all of these distortions vary over time in motion pictures, methods for determining a single objective picture quality value for this time varying distortion are examined. As a result, generally applicable objective picture quality scale is obtained that correlates extremely well with subjective picture quality scale for both still and motion pictures, irrespective of the contents of the pictures. Having an objective scale facilitates automated picture quality evaluation and control.

This paper discusses pulse responses of multi-conductor transmission lines terminated by linear and nonlinear subnetworks. At first step, the circuit is partitioned into a linear transmission lines and nonlinear subnetworks by the substitution voltage sources. Then, the linear subnetworks are solved by a well-known phasor technique, and the nonlinear subnetworks by a numerical integration technique. The variational value at each iteration is calculated by a frequency domain relaxation method to the associated linearized time-invariant sensitivity circuit. Although the algorithm can be efficiently applied to weakly nonlinear circuits, the convergence ratio for stiff nonlinear circuits becomes very small. Hence, we recommend to introduce a compensation element which plays very important role to weaken the nonlinearity. Thus, our algorithm is very simple and can be efficiently applied to wide classes of nonlinear circuits.

We introduce a generalized cln grammar (gclng), a generalization of a completely linearly nested context-free grammar (clncfg), of which variables are partitioned linearly and each rule satisfies similar conditions as those of clncfg related to its partition. We show that the class of languages generated by gclng's coincides with the class of quasi-rational languages, and consider the inclusion relations between languages generated by gclng's and those generated by clncfg's.

This paper proposes a new environment for high-level VLSI design specification validation using "Algorithmic Debugging" and evaluates its benefits on three significant examples (a protocol processor, an 8-bit CPU, and a Prolog processor). A design is specified at a high-level using the structured analysis (SA) method, which is useful for analyzing and understanding the functionality to be realized. The specification written in SA is transformed into a logic programming language and is simulated in it. The errors (which terminate with an incorrect output in the simulation) included in the three large examples are efficiently located by answering junt a few queries from the algorithmic debugger. The number of interactions between the designer and the debugger is reduced by a factor of ten to a hundred compared to conventional simulation based validation methodologies. The correct SA specification can be automatically translated into a Register Transfer Level (RTL) specification suitable for logic synthesis. In this environment, a designer is freed from the tedious task of debugging a RTL specification, and can concentrate on the design itself. This environment promises to be an important step towards efficient high-level VLSI design specification validation.

High performance I/O circuits for fast memory devices such as Synchronous DRAMs were studied. For a TTL interface, the effect of capacitive loading must increase as I/O speed is increased, and signal termination is required for frequencies over 100 MHz. For this reason, industry-proposed alternative interface approaches such as GTL and CTT were investigated using experimental test devices. The results showed that open-drain type drivers have a problem; as the frequency increases, the high-level output voltage becomes degraded. In contrast, a push-pull driver T-LVTTL (Terminated Low Voltage TTL), developed as an implementation of the CTT interface specification, was found to be suitable for high-speed data transfer. A high-speed bus driver circuit connecting an impedance element in series to the stub is proposed as an application of T-LVTTL. Simulated results showed that this scheme greatly improves the signal integrity of memory bus systems; the operating frequency could very well be the highest among several schemes discussed as candidates for the post-LVTTL standard interface.

The graph bisection problem is to partition a given graph into two subgraphs with equal size with minimizing the cutsize. This problem is NP-hard, and hence several heuristic algorithms have been proposed. Among them, the Kernighan-Lin algorithm and the Fiduccia-Mattheyses algorithm are well known, and widely used in practical applications. Since those algorithms are iterative improvement algorithms, in which the current solution is iteratively improved by interchanging a pair of two nodes belonging to different subgraphs, or moving one node from one subgraph to the other, those algorithms tend to fall into a local optimum. In this paper, we present a heuristic algorithm based on subgraph migration to avoid falling into a local optimum. In this algorithm, an initial solution is given, and it is improved by moving a subgraph, which is effective to reduce the cutsize. The algorithm repeats this operation until no further improvement can be achieved. Finally, the balance of the bisection is restored by moving nodes to get a final solution. Experimental results show that the proposed algorithm gets better solutions than the Kernighan-Lin and Fiduccia-Mattheyses algorithms.

For a CBR (Constant Bit Rate) connection in an ATM (Asynchronous Transfer Mode) network, we determine the CDV (Cell Delay Variation) tolerance for the mapping of ATM cells from the ATM Layer onto the Physical Layer. Our result will be useful to properly allocate resources to connections and to accurately enforce the contract governing the user's cell traffic by UPC (Usage Parameter Control).

This letter proposes a VP-shaper for ATM networks that controls the VC-level cell clumping. The new shaper is compared with a conventional shaper and is found to significantly increase CAC (Call Admission Control) efficiency and achieve high VP utilization gain. Hardware implementation based on a shared buffer and chained lists is presented and its feasibility is shown.

In this paper, chaos synchronization in coupled discrete-time dynamical systems is studied. Computer results display the interesting synchronization behaviors in the mutually coupled systems. As possible applications of chaos synchronization, parameter estimations and secure communications are proposed. Furthermore, a modified OGY method is given, which converts a chaotic motion into a periodic motion.

A new approach is described for the datapath scheduling of behavioral descriptions containing nested conditional branches of arbitrary structures. This paper first investigates such a complex scheduling mechanism, and formulates an optimal scheduling problem as a 0-1 integer programming problem such that given a prescribed number of control steps, the total cost of functional units can be minimized. In this formulation, each constraint is expressed in the form of a Boolean function, which is set equal to 1 or 0 according as the constraint is satisfied or not, respectively, and a satisfiability problem is defined by the product of the Boolean functions. A procedure is then described, which intends to seek an optimal solution by means of a branch-and-bound method on a binary decision diagram representing the satisfiability problem. Experimental results are also shown, which demonstrate that our approach is of more practical use than the existing methods.

A new approach to implement queues for controlling ATM switch LSI is presented. In many conventional architecture, external FIFOs are provided for each output link and used to manage the address of the buffer in an ATM switch. We reduce the number of FIFOs by using a self-timed queue with a search circuit that finds the earliest entry for each output link. Using this architecture, number of the FIFOs is reduced to 1/N, where N is the switch size. Delay priority and multicasting can be supported without doubling the number of the queues. This new queue can also be utilized as an ATM switch by itself. Evaluation chip was fabricated using 0.5-µm CMOS process technology. Inter-stage transfer speed over 500 MHz and cycle time over 125 MHz was obtained. This performance is enough for a 622-Mbps 1616 ATM Switch.

This paper presents the results of a study made to determine the line length coverage of the high-bit-rate digital subscriber line (HDSL) present in NTT's local networks. The HDSL carries one bi-directional 784 kbit/s channel per pair and supports the digital interface at 1544kbit/s by using two cable pairs. The primary purpose of this study is to estimate the range limits for candidate transmission schemes considering line installation conditions, and to determine the most promising transmission scheme and its feasibility given the environment of NTT's local networks. Pulse amplitude modulation (PAM) and quadrature amplitude modulation (QAM) transmission schemes are compared for HDSL implementation. It is shown that 2B1Q-PAM and 16-QAM generally achieve better performance than the more complicated PAM and QAM given the presence intra-system crosstalk interference (interference between identical transmission systems). The range limits determined by inter-system crosstalk interference (interference between different transmission systems) with basic rate access (BRA) implementing a burst-mode transmission method are also estimated. This paper concludes that 2B1Q-PAM achieves the best overall performance in NTT's local networks. A feasibility study of 192-6144 kbit/s transmission is also described.