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  • Enhanced TCP Congestion Control with Higher Utilization in Under-Buffered Links

    Dowon HYUN  Ju Wook JANG  

     
    LETTER-Network

      Vol:
    E95-B No:4
      Page(s):
    1427-1430

    TCP Reno is not fully utilized in under-buffered links. We propose a new TCP congestion control algorithm that can utilize the link almost up to 100% except the first congestion avoidance cycle. Our scheme estimates the minimum congestion window size for full link utilization in every congestion avoidance cycle and sends extra packets without touching TCP Reno congestion control. It has the same RTT fairness and the same saw-tooth wave as TCP Reno does. Our scheme does not affect competing TCP Reno flows since it uses only unused link capacity. We provide a simple mathematical modeling as well as ns-2 simulation results which show that the link utilization is improved by up to 19.88% for k=1/8 against TCP Reno when the buffer is k times the optimal buffer size. We claim that our scheme is useful for transmitting large amount of data in under-buffered links.

  • A Small-Area and Low-Power SoC for Less-Invasive Pressure Sensing Capsules in Ambulatory Urodynamic Monitoring

    Hirofumi IWATO  Keishi SAKANUSHI  Yoshinori TAKEUCHI  Masaharu IMAI  

     
    PAPER

      Vol:
    E95-C No:4
      Page(s):
    487-494

    To measure the detrusor pressure for diagnosing lower urinary tract symptoms, we designed a small-area and low-power System on a Chip (SoC). The SoC should be small and low power because it is encapsulated in tiny air-tight capsules which are simultaneously inserted in the urinary bladder and rectum for several days. Since the SoC is also required to be programmable, we designed an Application Specific Instruction set Processor (ASIP) for pressure measurement and wireless communication, and implemented almost required functions on the ASIP. The SoC was fabricated using a 0.18 µm CMOS mixed-signal process and the chip size is 2.5 2.5 mm2. Evaluation results show that the power consumption of the SoC is 93.5 µW, and that it can operate the capsule for seven days with a tiny battery.

  • An Area-Efficient Reconfigurable LDPC Decoder with Conflict Resolution

    Changsheng ZHOU  Yuebin HUANG  Shuangqu HUANG  Yun CHEN  Xiaoyang ZENG  

     
    PAPER

      Vol:
    E95-C No:4
      Page(s):
    478-486

    Based on Turbo-Decoding Message-Passing (TDMP) and Normalized Min-Sum (NMS) algorithm, an area efficient LDPC decoder that supports both structured and unstructured LDPC codes is proposed in this paper. We introduce a solution to solve the memory access conflict problem caused by TDMP algorithm. We also arrange the main timing schedule carefully to handle the operations of our solution while avoiding much additional hardware consumption. To reduce the memory bits needed, the extrinsic message storing strategy is also optimized. Besides the extrinsic message recover and the accumulate operation are merged together. To verify our architecture, a LDPC decoder that supports both China Multimedia Mobile Broadcasting (CMMB) and Digital Terrestrial/ Television Multimedia Broadcasting (DTMB) standards is developed using SMIC 0.13 µm standard CMOS process. The core area is 4.75 mm2 and the maximum operating clock frequency is 200 MHz. The estimated power consumption is 48.4 mW at 25 MHz for CMMB and 130.9 mW at 50 MHz for DTMB with 5 iterations and 1.2 V supply.

  • Energy Minimum Operation with Self Synchronous Gate-Level Autonomous Power Gating and Voltage Scaling

    Benjamin DEVLIN  Makoto IKEDA  Kunihiro ASADA  

     
    PAPER

      Vol:
    E95-C No:4
      Page(s):
    546-554

    A 65 nm self synchronous field programmable gate array (SSFPGA) which uses autonomous gate-level power gating with minimal control circuitry overhead for energy minimum operation is presented. The use of self synchronous signaling allows the FPGA to operate at voltages down to 370 mV without any parameter tuning. We show both 2.6x total energy reduction and 6.4x performance improvement at the same time for energy minimum operation compared to the non-power gated SSFPGA, and compared to the latest research 1.8x improvement in power-delay product (PDP) and 2x performance improvement. When compared to a synchronous FPGA in a similar process we are able to show up to 84.6x PDP improvement. We also show energy minimum operation for maximum throughput on the power gated SSFPGA is achieved at 0.6 V, 27 fJ/operation at 264 MHz.

  • OntoPop: An Ontology Population System for the Semantic Web

    Theerayut THONGKRAU  Pattarachai LALITROJWONG  

     
    PAPER

      Vol:
    E95-D No:4
      Page(s):
    921-931

    The development of ontology at the instance level requires the extraction of the terms defining the instances from various data sources. These instances then are linked to the concepts of the ontology, and relationships are created between these instances for the next step. However, before establishing links among data, ontology engineers must classify terms or instances from a web document into an ontology concept. The tool for help ontology engineer in this task is called ontology population. The present research is not suitable for ontology development applications, such as long time processing or analyzing large or noisy data sets. OntoPop system introduces a methodology to solve these problems, which comprises two parts. First, we select meaningful features from syntactic relations, which can produce more significant features than any other method. Second, we differentiate feature meaning and reduce noise based on latent semantic analysis. Experimental evaluation demonstrates that the OntoPop works well, significantly out-performing the accuracy of 49.64%, a learning accuracy of 76.93%, and executes time of 5.46 second/instance.

  • A Development of Game-Based Learning Environment to Activate Interaction among Learners

    Ryo TAKAOKA  Masayuki SHIMOKAWA  Toshio OKAMOTO  

     
    PAPER

      Vol:
    E95-D No:4
      Page(s):
    911-920

    Many studies and systems that incorporate elements such as “pleasure” and “fun” in the game to improve a learner's motivation have been developed in the field of learning environments. However, few are the studies of situations where many learners gather at a single computer and participate in a game-based learning environment (GBLE), and where the GBLE designs the learning process by controlling the interactions between learners such as competition, collaboration, and learning by teaching. Therefore, the purpose of this study is to propose a framework of educational control that induces and activates interaction between learners intentionally to create a learning opportunity that is based on the knowledge understanding model of each learner. In this paper, we explain the design philosophy and the framework of our GBLE called “Who becomes the king in the country of mathematics?” from a game viewpoint and describe the method of learning support control in the learning environment. In addition, we report the results of the learning experiment with our GBLE, which we carried out in a junior high school, and include some comments by a principal and a teacher. From the results of the experiment and some comments, we noticed that a game may play a significant role in weakening the learning relationship among students and creating new relationships in the world of the game. Furthermore, we discovered that learning support control of the GBLE has led to activation of the interaction between learners to some extent.

  • Toward the Decision Tree for Inferring Requirements Maturation Types

    Takako NAKATANI  Narihito KONDO  Junko SHIROGANE  Haruhiko KAIYA  Shozo HORI  Keiichi KATAMINE  

     
    PAPER

      Vol:
    E95-D No:4
      Page(s):
    1021-1030

    Requirements are elicited step by step during the requirements engineering (RE) process. However, some types of requirements are elicited completely after the scheduled requirements elicitation process is finished. Such a situation is regarded as problematic situation. In our study, the difficulties of eliciting various kinds of requirements is observed by components. We refer to the components as observation targets (OTs) and introduce the word “Requirements maturation.” It means when and how requirements are elicited completely in the project. The requirements maturation is discussed on physical and logical OTs. OTs Viewed from a logical viewpoint are called logical OTs, e.g. quality requirements. The requirements of physical OTs, e.g., modules, components, subsystems, etc., includes functional and non-functional requirements. They are influenced by their requesters' environmental changes, as well as developers' technical changes. In order to infer the requirements maturation period of each OT, we need to know how much these factors influence the OTs' requirements maturation. According to the observation of actual past projects, we defined the PRINCE (Pre Requirements Intelligence Net Consideration and Evaluation) model. It aims to guide developers in their observation of the requirements maturation of OTs. We quantitatively analyzed the actual cases with their requirements elicitation process and extracted essential factors that influence the requirements maturation. The results of interviews of project managers are analyzed by WEKA, a data mining system, from which the decision tree was derived. This paper introduces the PRINCE model and the category of logical OTs to be observed. The decision tree that helps developers infer the maturation type of an OT is also described. We evaluate the tree through real projects and discuss its ability to infer the requirements maturation types.

  • A C-Testable Multiple-Block Carry Select Adder

    Nobutaka KITO  Shinichi FUJII  Naofumi TAKAGI  

     
    PAPER-Dependable Computing

      Vol:
    E95-D No:4
      Page(s):
    1084-1092

    We propose a C-testable multiple-block carry select adder with respect to the cell fault model. Full adders and 2:1 multiplexers are considered as cells. By an additional external input, we obtain a C-testable carry select adder. We only modify the least significant position of each block. The adder is testable with a test set consisting of 16 patterns regardless of the size of each block and the number of blocks. This is the minimum test set for the adder. We show two gate-level implementations of the adder which are testable with a test set of 9 patterns and 7 patterns respectively, with respect to the single stuck-at fault model.

  • A Contrast Enhancement Method for HDR Image Using a Modified Image Formation Model

    Byoung-Ju YUN  Hee-Dong HONG  Ho-Hyoung CHOI  

     
    PAPER-Image Processing and Video Processing

      Vol:
    E95-D No:4
      Page(s):
    1112-1119

    Poor illumination and viewing conditions have negativeinfluences on the quality of an image, especially the contrast of the dark and bright region. Thus, captured and displayed images usually need contrast enhancement. Histogram-based or gamma correction-based methods are generally utilized for this. However, these methods are global contrast enhancement method, and since the sensitivity of the human eye changes locally according to the position of the object and the illumination in the scene, the global contrast enhancement methods have a limit. The spatial adaptive method is needed to overcome these limitations and it has led to the development of an integrated surround retinex (ISR), and estimation of dominant chromaticity (EDC) methods. However, these methods are based on Gray-World Assumption, and they use a general image formation model, so the color constancy is known to get poor results, shown through graying-out, halo-artifacts (ringing effects), and the dominated color. This paper presents a contrast enhancement method using a modified image formation model in which the image is divided into three components: global illumination, local illumination and reflectance. After applying the power constant value to control the contrast in the resulting image, the output image is obtained from their product to avoid or minimize a color distortion, based on the sRGB color representation. The experimental results show that the proposed method yields better performances than conventional methods.

  • Improving the Readability of ASR Results for Lectures Using Multiple Hypotheses and Sentence-Level Knowledge

    Yasuhisa FUJII  Kazumasa YAMAMOTO  Seiichi NAKAGAWA  

     
    PAPER-Speech and Hearing

      Vol:
    E95-D No:4
      Page(s):
    1101-1111

    This paper presents a novel method for improving the readability of automatic speech recognition (ASR) results for classroom lectures. Because speech in a classroom is spontaneous and contains many ill-formed utterances with various disfluencies, the ASR result should be edited to improve the readability before presenting it to users, by applying some operations such as removing disfluencies, determining sentence boundaries, inserting punctuation marks and repairing dropped words. Owing to the presence of many kinds of domain-dependent words and casual styles, even state-of-the-art recognizers can only achieve a 30-50% word error rate for speech in classroom lectures. Therefore, a method for improving the readability of ASR results is needed to make it robust to recognition errors. We can use multiple hypotheses instead of the single-best hypothesis as a method to achieve a robust response to recognition errors. However, if the multiple hypotheses are represented by a lattice (or a confusion network), it is difficult to utilize sentence-level knowledge, such as chunking and dependency parsing, which are imperative for determining the discourse structure and therefore imperative for improving readability. In this paper, we propose a novel algorithm that infers clean, readable transcripts from spontaneous multiple hypotheses represented by a confusion network while integrating sentence-level knowledge. Automatic and manual evaluations showed that using multiple hypotheses and sentence-level knowledge is effective to improve the readability of ASR results, while preserving the understandability.

  • Fast Hypercomplex Polar Fourier Analysis

    Zhuo YANG  Sei-ichiro KAMATA  

     
    LETTER-Image Processing and Video Processing

      Vol:
    E95-D No:4
      Page(s):
    1166-1169

    Hypercomplex polar Fourier analysis treats a signal as a vector field and generalizes the conventional polar Fourier analysis. It can handle signals represented by hypercomplex numbers such as color images. Hypercomplex polar Fourier analysis is reversible that means it can reconstruct image. Its coefficient has rotation invariance property that can be used for feature extraction. However in order to increase the computation speed, fast algorithm is needed especially for image processing applications like realtime systems and limited resource platforms. This paper presents fast hypercomplex polar Fourier analysis based on symmetric properties and mathematical properties of trigonometric functions. Proposed fast hypercomplex polar Fourier analysis computes symmetric points simultaneously, which significantly reduce the computation time.

  • Outband Sensing-Based Dynamic Frequency Selection (DFS) Algorithm without Full DFS Test in IEEE 802.11h Protocol

    Jaemin JEUNG  Seungmyeong JEONG  Jaesung LIM  

     
    LETTER

      Vol:
    E95-B No:4
      Page(s):
    1295-1296

    We propose an outband sensing-based IEEE 802.11h protocol without a full dynamic frequency selection (DFS) test. This scheme has two features. Firstly, every station performs a cooperative outband sensing, instead of inband sensing during a quiet period. And secondly, as soon as a current channel becomes bad, every station immediately hops to a good channel using the result of outband sensing. Simulation shows the proposed scheme increases network throughput against the legacy IEEE 802.11h.

  • A 580 fs-Resolution Time-to-Digital Converter Utilizing Differential Pulse-Shrinking Buffer Ring in 0.18 µm CMOS Technology

    Tetsuya IIZUKA  Satoshi MIURA  Ryota YAMAMOTO  Yutaka CHIBA  Shunichi KUBO  Kunihiro ASADA  

     
    PAPER

      Vol:
    E95-C No:4
      Page(s):
    661-667

    This paper proposes a sub-ps resolution TDC utilizing a differential pulse-shrinking buffer ring. This scheme uses two differentially-operated pulse-shrinking inverters and the TDC resolution is finely controlled by the transistor size ratio between them. The proposed TDC realizes 9 bit, 580 fs resolution in a 0.18 µm CMOS technology with 0.04 mm2 area, and achieves DNL and INL of +0.8/-0.8LSB and +4.3/-4.0LSB, respectively, without linearity calibration. A power dissipation at 1.5 MS/s ranges from 10.8 to 12.6 mW depending on the input time intervals.

  • All-Digital PMOS and NMOS Process Variability Monitor Utilizing Shared Buffer Ring and Ring Oscillator

    Tetsuya IIZUKA  Kunihiro ASADA  

     
    PAPER

      Vol:
    E95-C No:4
      Page(s):
    627-634

    This paper proposes an all-digital process variability monitor based on a shared structure of a buffer ring and a ring oscillator. The proposed circuit monitors the PMOS and NMOS process variabilities independently according to a count number of a single pulse which propagates on the ring during the buffer ring mode, and an oscillation period during the ring oscillator mode. Using this shared-ring structure, we reduce the occupation area about 40% without loss of process variability monitoring properties compared with the conventional circuit. The proposed shared-ring circuit has been fabricated in 65 nm CMOS process and the measurement results with two different wafer lots show the feasibility of the proposed process variability monitoring scheme.

  • FOREWORD Open Access

    Kazuhiro UEHARA  

     
    FOREWORD

      Vol:
    E95-B No:4
      Page(s):
    1035-1035
  • High Uniqueness Arbiter-Based PUF Circuit Utilizing RG-DTM Scheme for Identification and Authentication Applications

    Mitsuru SHIOZAKI  Kota FURUHASHI  Takahiko MURAYAMA  Akitaka FUKUSHIMA  Masaya YOSHIKAWA  Takeshi FUJINO  

     
    PAPER

      Vol:
    E95-C No:4
      Page(s):
    468-477

    Silicon Physical Unclonable Functions (PUFs) have been proposed to exploit inherent characteristics caused by process variations, such as transistor size, threshold voltage and so on, and to produce an inexpensive and tamper-resistant device such as IC identification, authentication and key generation. We have focused on the arbiter-PUF utilizing the relative delay-time difference between the equivalent paths. The conventional arbiter-PUF has a technical issue, which is low uniqueness caused by the ununiformity on response-generation. To enhance the uniqueness, a novel arbiter-based PUF utilizing the Response Generation according to the Delay Time Measurement (RG-DTM) scheme, has been proposed. In the conventional arbiter-PUF, the response 0 or 1 is assigned according to the single threshold of relative delay-time difference. On the contrary, the response 0 or 1 is assigned according to the multiple threshold of relative delay-time difference in the RG-DTM PUF. The conventional and RG-DTM PUF were designed and fabricated with 0.18 µm CMOS technology. The Hamming distances (HDs) between different chips, which indicate the uniqueness, were calculated by 256-bit responses from the identical challenges on each chip. The ideal distribution of HDs, which indicates high uniqueness, is achieved in the RG-DTM PUF using 16 thresholds of relative delay-time differences. The generative stability, which is the fluctuation of responses in the same environment, and the environmental stability, which is the changes of responses in the different environment were also evaluated. There is a trade-off between high uniqueness and high stability, however, the experimental data shows that the RG-DTM PUF has extremely smaller false matching probability in the identification compared to the conventional PUF.

  • Data Rate Limitations in Feedback Control over Networks

    Hideaki ISHII  Koji TSUMURA  

     
    INVITED PAPER

      Vol:
    E95-A No:4
      Page(s):
    680-690

    This paper provides an overview on the recent research on networked control with an emphasis on the tight relation between the two fields of control and communication. In particular, we present several results focusing on data rate constraints in networked control systems, which can be modeled as quantization of control-related signals. The motivation is to reduce the amount of data rate as much as possible in obtaining control objectives such as stabilization and control performance under certain measures. We also discuss some approaches towards control problems based on techniques from signal processing and information theory.

  • Optimization-Based Synthesis of Self-Triggered Controllers for Networked Systems

    Koichi KOBAYASHI  Kunihiko HIRAISHI  

     
    PAPER

      Vol:
    E95-A No:4
      Page(s):
    691-696

    In this paper, for networked systems, synthesis of self-triggered controllers is addressed. In the proposed method, the control input and the sampling time such that a given cost function is minimized are computed simultaneously. First, the optimal control problem of continuous-time linear systems is rewritten as that of systems with integral continuous-time dynamics. Next, this problem is approximately reduced to a linear programming problem. The proposed method can be applied to model predictive control. Finally, the effectiveness of the proposed method is shown by a numerical example.

  • A Robust Cooperative Spectrum Sensing Based on Kullback-Leibler Divergence

    Hiep VU-VAN  Insoo KOO  

     
    LETTER

      Vol:
    E95-B No:4
      Page(s):
    1286-1290

    Reliable detection of the licensed user signal is a pre-requirement for avoiding interference to the licensed user in a CR network. Cooperative spectrum sensing (CSS) is able to offer improved sensing performance compared to individual sensing. In this paper, we propose a robust soft combination rule based on the Kullback-Leibler divergence (KL-divergence) for CSS. The proposed scheme is able to obtain a similar sensing performance compared to that of maximum gain combination (MGC) without requiring signal to noise ratio (SNR) information. In addition, the proposed scheme protects the sensing process against common types of malicious users without a malicious user identification step. The simulation results demonstrate the effectiveness of the proposed scheme.

  • Improved Power Saving Mechanism to Increase Unavailability Interval in IEEE 802.16e Networks

    Kyunghye LEE  Youngsong MUN  

     
    LETTER-Network

      Vol:
    E95-B No:4
      Page(s):
    1414-1418

    To manage limited energy resources efficiently, IEEE 802.16e specifies sleep mode operation. Since there can be no communication between the mobile station (MS) and the serving base station (BS) during the unavailability interval, the MS can power down its physical operation components. We propose an improved power saving mechanism (iPSM) which effectively increases the unavailability interval of Type I and Type II power saving classes (PSCs) activated in an MS. After investigating the number of frames in the unavailability interval of each Type II PSC when used with Type I PSC, the iPSM chooses the Type II PSC that yields the maximum number of frames in the unavailability interval. Performance evaluation confirms that the proposed scheme is very effective.

12961-12980hit(42807hit)