This paper proposes a utility function-based scheduling algorithm for integrated real-time and non-real-time services in long-term evolution systems. The proposed utility function satisfies the target dropping ratio of real-time users; it uses the delay constraint and increases the throughput of non-real-time users by scheduling real-time users together with non-real-time users. Simulation results show that the proposed scheduling algorithm significantly improves the throughput of non-real-time users without sacrificing the quality of service of real-time users.

We consider secure wireless communications, where a source is communicating to a destination in the presence of K (K > 1) eavesdroppers. The source and destination both are equipped with multiple antennas, while each eavesdropper has a single antenna. The source aims to maximize the communication rate to the destination, while concealing the message from all the eavesdroppers. Combined with selective diversity, we propose a heuristic secrecy transmission scheme where the multiple-input-multiple-output (MIMO) secrecy channel is simplified into a multiple-input-single-output (MISO) one with the highest orthogonality to the eavesdropper channels. Then convex optimization is applied to obtain the optimal transmit covariance matrix for this selected MISO secrecy channel. Numerical results are provided to illustrate the efficacy of the proposed scheme.

An FPGA plays an essential role in industrial products due to its fast, stable and flexible features. But the power consumption of FPGAs used in portable devices is one of critical issues. Top-down hierarchical design method is commonly used in both ASIC and FPGA design. But, in the case where plural modules are integrated in an FPGA and some of them might be in sleep-mode, current FPGA architecture cannot be fully effective. In this paper, coarse-grained power gating FPGA architecture is proposed where a whole area of an FPGA is partitioned into several regions and power supply is controlled for each region, so that modules in sleep mode can be effectively power-off. We also propose a region oriented FPGA placement algorithm fitted to this user's hierarchical design based on VPR [1]. Simulation results show that this proposed method could reduce power consumption of FPGA by 38% on average by setting unused modules or regions in sleep mode.

Nowadays, a user authentication is very important in network environments. For safe authentication, they came up with six essential conditions in earlier studies. And a variety of mechanisms is presented by research scientists. However, they could not achieve the PFS. Because, though all these schemes are assumed that the communication between a smart card and a host is safe, actually it is not. Therefore, in this paper, we will point out what the communication between a smart card and a host is not safe, and propose a new user authentication mechanism that can reach to the PFS. And also, an encryption algorithm is used about 45% less than earlier studies in our proposed scheme. Thus, we can say that enhance the efficiency.

A new near-field source localization algorithm based on a uniform linear array was proposed. The proposed algorithm estimates each parameter separately but does not need pairing parameters. It can be divided into two important steps. The first step is bearing-related electric angle estimation based on the ESPRIT algorithm by constructing a special cumulant matrix. The second step is the other electric angle estimation based on the 1-D MUSIC spectrum. It offers much lower computational complexity than the traditional near-field 2-D MUSIC algorithm and has better performance than the high-order ESPRIT algorithm. Simulation results demonstrate that the performance of the proposed algorithm is close to the Cramer-Rao Bound (CRB).

To assess the performance of maximum-likelihood (ML) based Nakagami m parameter estimators, current methods rely on Monte Carlo simulation. In order to enable the analytical performance evaluation of ML-based m parameter estimators, we study the statistical properties of a parameter Δ, which is defined as the log-ratio of the arithmetic mean to the geometric mean for Nakagami-m fading power. Closed-form expressions are derived for the probability density function (PDF) of Δ. It is found that for large sample size, the PDF of Δ can be well approximated by a two-parameter Gamma PDF.

This paper suggests an outphasing scheme to reduce adjacent channel spectral regrowth triggered by the gain and phase mismatch between two signal paths in linear amplification with nonlinear component (LINC) systems. The error vector magnitude and power spectral density of the output signal considering path mismatch are described analytically using path mismatch factor. An outphasing scheme is proposed to reduce the spectral regrowth. The proposed outphasing scheme reshapes the phases of the separated signals in LINC systems to reduce the changes of the phases. Its performance is verified by performing simulations with multi-tone signals. The result shows that the scheme can reduce the spectral regrowth of the multi-tone signals significantly compared to the conventional outphasing scheme for LINC systems with path imbalance.

This letter focuses on the performance analysis on the Adaptive Sidelobe Blanker (ASB) detection algorithm in homogeneous environments, and provides closed summation expressions for Probability of Detection (PD) and Probability of False Alarm (PFA) rate in terms of hypergeometric function. The derived results are more powerful and effective than previous integral ones. Moreover, the framework can be modified to solve the the performance analysis problem involving in F or/and beta distributions. Several numerical evaluations of the convergence rate and computation time are provided and discussed.

A Mur type analytical absorbing boundary condition (A-ABC), which is based on the one-dimensional one-way wave equation, is proposed for multidimensional wave analysis by introducing the directional splitting technique. This new absorbing boundary condition is expansion of the first-order Mur. The absorbing ability, required memory, and calculation speed of the Mur type A-ABC are evaluated by comparison with those of conventional ABCs. The result indicated that absorbing ability of the proposed ABC is higher than the first-order Mur and lower than the second-order Mur at large incident angle. While, our proposed ABC has advantage in both required memory and calculation speed by comparison with the second-order Mur. Thus, effectivity of the proposed Mur type A-ABC is shown.

This letter proposes a practical algorithm for video transmission of the scalable extension of H.264/AVC (SVC) over limited bit-rate and varying channel signal-to-noise ratio (SNR). The proposal consists of SVC source-layer dropping and layered FEC using LDPC codes to maximize the video quality. The experimental results show that the proposed method realizes better video quality than the compared unequal error protection (UEP) without source-layer dropping. This implies that the dropping of a certain number of source-layers and using the resultant bit-budget for channel coding is more effective than the other UEP case which uses all possible source-layers.

We demonstrate the wavelength trimming of MEMS VCSELs by etching a cantilever-shaped top mirror using FIB etching. The proposed technique can be used for the post-process precise wavelength allocation of athermal MEMS VCSELs. The modeling and experimental results on 850 nm MEMS VCSELs are presented. The results show a possibility of realizing both red-shift and blue-shift wavelength changes by choosing the etching area of the cantilever.

We have developed two modulator driver ICs that are based on the functional distributed circuit (FDC) topology for over 40-Gb/s optical transmission systems using InP HBT technology. The FDC topology enables both a wide bandwidth amplifier and high-speed digital functions. The none-return-to-zero (NRZ) driver IC, which is integrated with a D-type flip-flop, exhibits 2.6-Vp-p (differential output: 5.2 Vp-p) output-voltage swings with a high signal quality at 43 and 50 Gb/s. The return-to-zero (RZ) driver IC, which is integrated with a NRZ to RZ converter, produces 2.4-Vp-p (differential output: 4.8 Vp-p) output-voltage swings and excellent eye openings at 43 and 50 Gb/s. Furthermore, we conducted electro-optical modulation experiments using the developed modulator driver ICs and a dual drive LiNbO3 Mach-Zehnder modulator. We were able to obtain NRZ and RZ clear optical eye openings with low jitters and sufficient extinction ratios of more than 12 dB, at 43 and 50 Gb/s. These results indicate that the FDC has the potential to achieve a large output voltage and create high-speed functional ICs for over-40-Gb/s transmission systems.

This paper presents an ultra-wideband (UWB) bandpass filter (BPF) with sharp attenuation slope characteristics. The circuit structure consists of an inter-digital finger resonator, parallel-coupled lines and phase matching line. The design of the bandwidth was described by using the even and odd mode characteristic impedances in the resonator structure. The parallel-coupled lines were also designed in the same manner. The parameters of the resonator and two parallel-coupled lines in combination as the BPF were then optimized by the simulation with HFSS. The designed BPF was experimentally fabricated and its measured performances showed the bandwidth from 3.6 to 10 GHz with the 20 dB outband rejection. For the U.S. UWB band design, the matching line was inserted between the two parallel-coupled lines. The matching at both band edges was then qualitatively analyzed on the smithchart. The HFSS simulation results of the structure realized the bandwidth from 3.1 to 10.6 GHz with sharp attenuation slope characteristics for SWR < 2.0. The measurement results agree well with the simulation results.

Modern FPGAs (Field Programmable Gate Arrays), such as Xilinx Virtex-4, have the capability of changing their contents dynamically and partially, allowing implementation of such concepts as a HW (hardware) task. Similarly to its software counterpart, the HW task shares time-multiplexed resources with other HW tasks. To support preemptive multitasking in such systems, additional context saving and restoring mechanisms must be built practically from scratch. This paper presents an efficient method for hardware task preemption which is suitable for tasks containing both Flip-Flops and memory elements. Our solution consists of an offline tool for analyzing and manipulating bitstreams, used at the design time, as well as an embedded system framework. The framework contains a DMA-based (Direct Memory Access), instruction-driven reconfiguration/readback controller and a developed lightweight bus facilitating management of HW tasks. The whole system has been implemented on top of the Xilinx Virtex-4 FPGA and showed promising results for a variety of HW tasks.

We propose a novel 13 planar optical switch using aspheric lenses and carrier-induced tunable prisms on InP. An input light beam is collimated by the aspheric lenses in a slab waveguide. The tunable prism, whose refractive indices are tuned by the carrier plasma effect, deflect the collimated light beam and guide it to the output ports. The switching operations of the 13 optical switch that consists of five lenses and eight prisms with a footprint of 5003500 µm are performed by three-dimensional beam propagation methods. A static switching operation with a 5-dB insertion loss and a 13-dB extinction ratio is obtained with 70-mA current injection for each prism. This device has a simple structure and low power consumption and may be useful for optical packet switching systems.

Wireless sensor network MAC protocols switch radios off periodically, employing the so-called duty cycle mechanism, in order to conserve battery power that would otherwise be wasted by energy-costly idle listening. In order to minimize the various negative side-effects of the original scheme, especially on latency and throughput, various improvements have been proposed. In this paper, we introduce a new MAC protocol called MAC2(Multi-hop Adaptive with packet Concatenation-MAC) which combines three promising techniques into one protocol. Firstly, the idea to forward packets over multiple hops within one operational cycle as initially introduced in RMAC. Secondly, an adaptive method that adjusts the listening period according to traffic load minimizing idle listening. Thirdly, a packet concatenation scheme that not only increases throughput but also reduces power consumption that would otherwise be incurred by additional control packets. Furthermore, MAC2 incorporates the idea of scheduling data transmissions with minimum latency, thereby performing packet concatenation together with the multi-hop transmission mechanism in a most efficient way. We evaluated MAC2 using the prominent network simulator ns-2 and the results show that our protocol can outperform DW-MAC – a state of the art protocol both in terms of energy efficiency and throughput.

The evolution of Internet, the growth of Internet users and the new enabled technological capabilities place new requirements to form the Future Internet. Many features improvements and challenges were imposed to build a better Internet, including securing roaming of data and services over multiple administrative domains. In this research, we propose a multi-domain access control infrastructure to authenticate and authorize roaming users through the use of the Diameter protocol and EAP. The Diameter Protocol is a AAA protocol that solves the problems of previous AAA protocols such as RADIUS. The Diameter EAP Application is one of Diameter applications that extends the Diameter Base Protocol to support authentication using EAP. The contributions in this paper are: 1) first implementation of Diameter EAP Application, called DiamEAP, capable of practical authentication and authorization services in a multi-domain environment, 2) extensibility design capable of adding any new EAP methods, as loadable plugins, without modifying the main part, and 3) provision of EAP-TLS plugin as one of the most secure EAP methods. DiamEAP Server basic performances were evaluated and tested in a real multi-domain environment where 200 users attempted to access network using the EAP-TLS method during an event of 4 days. As evaluation results, the processing time of DiamEAP using the EAP-TLS plugin for authentication of 10 requests is about 20 ms while that for 400 requests/second is about 1.9 second. Evaluation and operation results show that DiamEAP is scalable and stable with the ability to handle more than 6 hundreds of authentication requests per second without any crashes. DiamEAP is supported by the AAA working group of the WIDE Project.

A technique to reduce noise transfer functions (NTF) of switched-capacitor (SC) integrators without changing their signal transfer functions (STF) is proposed. The proposed technique based on a simple reconnection scheme of multiple sampling capacitors. It can be implemented into any SC integrators as long as they have a transfer delay. A design strategy is also given to reduce the effect of parasitic capacitors. An SC integrator with a small total capacitance and a low noise transfer gain based on the proposed technique is also proposed. For a given design example, the total capacitance and the simulated noise transfer gain of the proposed SC integrator are 37% and 90% less than the conventional one.

This paper presents an area-effective bandwidth enhancement technique using interwoven inductors. Inductive peaking is a common practice for bandwidth enhancement, however the area overhead of inductors is a serious issue. We implement six or four inductors into an interwoven inductor. Furthermore parasitics of the inductors can be reduced. The proposed inductor is applied to a laser-diode driver in a 0.18 µm CMOS. Compared to conventional shunt-peaking, the proposed circuit achieves 1.6 times faster operation and 60% reduction in power consumption under the condition for the same amount of data transmission and the LD driving current. The interwoven inductor can reduce the circuit area by 26%. Parasitic capacitance in interwoven inductor is discussed. Simulation results reveal that line-to-line capacitance is a significant factor on bandwidth degradation.

This paper proposes a dual-conduction class-C VCO for ultra-low supply voltages. Two cross-coupled NMOS pairs with different bias points are employed. These NMOS pairs realize an impulse-like current waveform to improve the phase noise in the low supply conditions. The proposed VCO was implemented in a standard 0.18 µm CMOS technology, which oscillates at a carrier frequency of 4.5 GHz with a 0.2-V supply voltage. The measured phase noise is -104 dBc/Hz@1 MHz-offset with a power consumption of 114 µW, and the FoM is -187 dBc/Hz.