In this paper, we propose a synthesis method for asynchronous circuits with bundled-data implementation. The proposed method iteratively applies behavioral synthesis and floorplanning to obtain a near optimum circuit in the term of latency under given design constraints. To improve latency, behavioral synthesis and floorplanning are carried out so that the delay of the control circuit is minimized and the addition of delay elements to satisfy timing constraints is minimized. We evaluate the effectiveness of the proposed method in terms of latency, area, and the number of timing violations while synthesizing several benchmarks. Experimental results show that the proposed method synthesizes faster circuits compared to the circuit synthesized without the proposed method. Also, the proposed method is effective to reduce the number of timing violations.

The cause-and-effect relation between plasmon-resonance absorption and surface wave in a sinusoidal metal grating is investigated. By introducing an equivalent impedance model, similar to an equivalent circuit on an electric circuit, which is an impedance boundary value problem on the fictitious surface over the grating, we estimate the surface wave from the eigen field of the model by using the resonance property of the scattered field. Through numerical examples, we illustrate that the absorption in the grating occurs in the condition of exciting the surface wave along the model, and the real part of the surface impedance is negative on about half part of the fictitious surface in the condition.

We previously proposed a unified wireless system called “Flexible Wireless System”. Comprising of flexible access points and a flexible signal processing unit, it collectively receives a wideband spectrum that includes multiple signals from various wireless systems. In cases of simultaneous multiple signal reception, however, reception performance degrades due to the interference among multiple signals. To address this problem, we propose a new signal separation and reconstruction method for spectrally overlapped signals. The method analyzes spectral information obtained by the short-time Fourier transform to extract amplitude and phase values at each center frequency of overlapped signals at a flexible signal processing unit. Using these values enables signals from received radio wave data to be separated and reconstructed for simultaneous multi-system reception. In this paper, the BER performance of the proposed method is evaluated using computer simulations. Also, the performance of the interference suppression is evaluated by analyzing the probability density distribution of the amplitude of the overlapped interference on a symbol of the received signal. Simulation results confirmed the effectiveness of the proposed method.

In cognitive radio networks, secondary users exchange control information to utilize the available channels efficiently, to maintain connectivity, to negotiate for data communication such as sender-receiver handshakes, for neighbor discovery etc. This task is not trivial in cognitive radio networks due to the dynamic nature of network environment. Generally, this problem is tackled by using two famous approaches. The first one is the use of common control channel (CCC) and the second one is using channel hopping (a.k.a sequence-based protocols). The use of CCC simplifies the processes of MAC protocols. However, it may not be feasible in cognitive radio networks as the available channels, including control channel, are dynamically changing according to primary user activities. Channel hopping approaches can tolerate the failure of network due to primary user activities. But it causes significant amount of channel access delay which is known as time to rendezvous (TTR). In this paper, we propose a hybrid protocol of these two mechanisms. This hybrid protocol can maintain connectivity and it can guarantee the secondary users to be able to exchange necessary control information in dynamic environment. In our hybrid protocol, we use multiple control channels. If some control channels are unavailable in case of primary user appearances, secondary users still can communicate on different control channels, so it can be more tolerable primary user activities than normal CCC approaches. Channel hopping is performed only for control channels, so it provides relatively small amount of channel access delay.

An H.264/AVC encoder LSI (named “SARA”) that supports High422 profile, as well as 422 profile of MPEG-2, has been developed for HDTV broadcasting infrastructures. It contains three motion estimation and compensation (ME/MC) engines with wide search ranges of -217.75 to +199.75 horizontally, -109.75 to +145.75 vertically, which can utilize almost all H.264/AVC ME/MC coding tools, such as multiple reference frame, variable block size, quarter-pel prediction, macroblock adaptive field/frame prediction (MBAFF), spatial/temporal direct mode, and weighted prediction. Our evaluations show that it can encode fast moving scenes with 1.2 dB to 1.7 dB higher than the JM. It was successfully fabricated in a 90-nm technology, and integrates 140 million transistors.

Fidelity Range Extension (FRExt) (i.e. High Profile) was added to the H.264/AVC recommendation in the second version. One of the features included in FRExt is the Adaptive Block-size Transform (ABT). In order to conform to the FRExt, a Fractional Motion Estimation (FME) architecture is proposed to support the 88/44 adaptive Hadamard Transform (88/44 AHT). The 88/44 AHT circuit contributes to higher throughput and encoding performance. In order to increase the utilization of SATD (Sum of Absolute Transformed Difference) Generator (SG) in unit time, the proposed architecture employs two 8-pel interpolators (IP) to time-share one SG. These two IPs can work in turn to provide the available data continuously to the SG, which increases the data throughput and significantly reduces the cycles that are needed to process one Macroblock. Furthermore, this architecture also exploits the linear feature of Hadamard Transform to generate the quarter-pel SATD. This method could help to shorten the long datapath in the second-step of two-iteration FME algorithm. Finally, experimental results show that this architecture could be used in the applications requiring different performances by adjusting the supported modes and operation frequency. It can support the real-time encoding of the seven-mode 4 K2 K@24 fps or six-mode 4 K2 K@30 fps video sequences.

Hybrid wired/wireless on-chip network is a promising communication architecture for multi-/many-core SoC. For application-specific SoC design, it is important to design a dedicated on-chip network architecture according to the application-specific nature. In this paper, we propose a heuristic wireless link allocation algorithm for creating hybrid on-chip network architecture. The algorithm can eliminate the performance bottleneck by replacing multi-hop wired paths by high-bandwidth single-hop long-range wireless links. The simulation results show that the hybrid on-chip network designed by our algorithm improves the performance in terms of both communication delay and energy consumption significantly.

Network-on-Chips (NoCs) have been proposed as a solution for addressing the global communication challenges in System-on-Chip (SoC) architectures that are implemented in nanoscale technologies. For the use of NoCs to be feasible in today's industrial designs, a custom-tailored, power- efficient NoC topology that satisfies the application characteristics is required. In this work, we present a design methodology that automates the synthesis of such application-specific NoC topologies. We present a method which integrates partitioning into floorplanning phase to explore optimal clustering of cores during floorplanning with minimized link and switch power consumption. Based on the size of applications, we also present an Integer Linear Programming and a heuristic method to place switches and network interfaces on the floorplan. Then, a power and timing aware path allocation algorithm is carried out to determine the connectivity across different switches. We perform experiments on several SoC benchmarks and present a comparison with the latest work. For small applications, the NoC topologies synthesized by our method show large improvements in power consumption (27.54%), hop-count (4%) and running time (66%) on average. And for large applications, the synthesized topologies result in large power (31.77%), hop-count (29%) and running time (94.18%) on average.

Three types of electron injection scheme: both side injection scheme and self-repair one side injection scheme Type A (injection for once) and Type B (injection for twice) are proposed and analyzed comprehensively for 65 nm technology node 6T- and 8T-SRAM cells to find the optimum injection scheme and cell architecture. It is found that the read speed degrades by as much as 6.3 times in the 6T-SRAM with the local injected electrons. However, the read speed of the 8T-SRAM cell does not degrade because the read port is separated from the write pass gate transistors. Furthermore, the self-repair one side injection scheme is most suitable to solve the conflict of the half select disturb and write characteristics. The worst cell characteristics of Type A and Type B self-repair one side injection schemes were found to be the same. In the self-repair one side injection 8T-SRAM, the disturb margin increases by 141% without write margin or read speed degradation. The proposed schemes have no process or area penalty compared with the standard CMOS-process.

This paper presents analysis and design of a new ultra-low voltage analog front end (AFE) dedicated to strain sensor applications. The AFE, designed in 0.18 µm CMOS process, features a chopper-stabilized instrumentation amplifier (IA), a balanced active MOSFET-C 2nd order low pass filter (LPF), a clock generator and a voltage booster which operate at supply voltage (Vdd) of 0.6 V. The designed IA achieves 30 dB of closed-loop gain, 101 dB of common-mode rejection ratio (CMRR) at 50 Hz, 80 dB of power-supply rejection ratio (PSRR) at 50 Hz, thermal noise floor of 53.4 nV/, current consumption of 14 µA, and noise efficiency factor (NEF) of 9.7. The high CMRR and rail-to-rail output swing capability is attributed to a new low voltage realization of the active-bootstrapped technique using a pseudo-differential gain-boosting operational transconductance amplifier (OTA) and proposed current-driven bulk (CDB) biasing technique. An output capacitor-less low-dropout regulator (LDO), with a new fast start-up LPF technique, is used to regulate this 0.6 V supply from a 0.8–1.0 V energy harvesting power source. It achieves power supply rejection (PSR) of 42 dB at frequency of 1 MHz. A cascode compensated pseudo differential amplifier is used as the filter's building block for low power design. The filter's single-ended-to-balanced converter is implemented using a new low voltage amplifier with two-stage common-mode cancellation. The overall AFE was simulated to have 65.6 dB of signal-to-noise ratio (SNR), total harmonic distortion (THD) of less than 0.9% for a 100 Hz sinusoidal maximum input signal, bandwidth of 2 kHz, and power consumption of 51.2 µW. Spectre RF simulations were performed to validate the design using BSIM3V3 transistor models provided by GLOBALFOUNDRIES 0.18 µm CMOS process.

An adaptive rate controller (ARC) based on an adaptive neural fuzzy inference system (ANFIS) is designed to autonomously adjust the data rate of a mobile heterogeneous network to adapt to the changing traffic load and the user speed for multimedia call services. The effect of user speed on the handoff rate is considered. Through simulations, it has been demonstrated that the ANFIS-ARC is able to maintain new call blocking probability and handoff failure probability of the mobile heterogeneous network below a prescribed low level over different user speeds and new call origination rates while optimizing the average throughput. It has also been shown that the mobile cognitive wireless network with the proposed CS-ANFIS-ARC protocol can support more traffic load than neural fuzzy call-admission and rate controller (NFCRC) protocol.

We provide a theoretical analysis of the capacity achievable by an open/closed-access cognitive radio system, where the system uses spectrum resources primarily allocated to a macro cellular system. For spectrum sharing, we consider two methods based on listen-before-talk and adaptive transmit power control principles. Moreover, outdoor and indoor installations of CRS stations are investigated. We have also taken the effect of antenna heights into consideration. Numerical results reveal the capacities possible from CRS base stations installed within the coverage area of the macro cell system. We show numerical examples that compare the capacities achievable by open-access and closed access cognitive radio systems.

This letter is concerned with cellular controlled short-range communication (CCSRC) systems, which can provide a significant performance gain over the traditional cellular systems as shown in the literature. However, to obtain such a gain, CCSRC systems need perfect channel state information (CSI) of all users and the complexity of setting up the optimal cooperative clusters is factorial with respect to the number of potentially cooperative users, which is very unrealistic in practical systems. To solve this problem, we propose a novel cooperative strategy, where CCSRC systems only need the distances between all user pairs and the complexity of setting up the cooperative clusters is relatively low. Simulation results show that the performance of the proposed strategy is close to optimal.

This paper proposes an S-parameter analysis method that uses simultaneous excitation for multi-antenna systems. In this method, OFDM (Orthogonal Frequency Division Multiplexing) and CI (Carrier Interferometry) pulse generation schemes are employed for maintaining the orthogonality among the excited signals. In OFDM excitation schemes, the characteristics of the neighboring antennas can be calculated by assigning different frequency subcarriers exclusively. CI enables the simultaneous verification of the antennas distant enough since this method can provide temporal orthogonality. Combining these two methods yields the simultaneous analyses of array antennas with both narrow and wide element spacing. The simulation of a 22 multi-antenna shows that the results of the proposed method agree well with those of the conventional method even though its computation speed is more 4 times that of the conventional method.

By using a quadratic compensation slope, a CMOS current-mode buck DC-DC converter with constant frequency characteristics over wide input and output voltage ranges has been developed. The use of a quadratic slope instead of a conventional linear slope makes both the damping factor in the transfer function and the frequency bandwidth of the current feedback loop independent of the converter's output voltage settings. When the coefficient of the quadratic slope is chosen to be dependent on the input voltage settings, the damping factor in the transfer function and the frequency bandwidth of the current feedback loop both become independent of the input voltage settings. Thus, both the input and output voltage dependences in the current feedback loop are eliminated, the frequency characteristics become constant, and the frequency bandwidth is maximized. To verify the effectiveness of a quadratic compensation slope with a coefficient that is dependent on the input voltage in a buck DC-DC converter, we fabricated a test chip using a 0.18 µm high-voltage CMOS process. The evaluation results show that the frequency characteristics of both the total feedback loop and the current feedback loop are constant even when the input and output voltages are changed from 2.5 V to 7 V and from 0.5 V to 5.6 V, respectively, using a 3 MHz clock.

A novel high speed 4-2 compressor using static and pass-transistor logic, has been designed in a 0.35 µm CMOS technology. In order to reduce gate level delay and increase the speed, some changes are performed in truth table of conventional 4-2 compressor which leaded to the simplification of logic function for all parameters. Therefore, power dissipation is decreased. In addition, because of similar paths from all inputs to the outputs, the delays are the same. So there will be no need for extra buffers in low latency paths to equalize the delays.

We present an economical and fault-tolerant load balancing strategy (EFTLBS) based on an operator replication mechanism and a load shedding method, that fully utilizes the network resources to realize continuous and highly-available data stream processing without dynamic operator migration over wide area networks. In this paper, we first design an economical operator distribution (EOD) plan based on a bin-packing model under the constraints of each stream bandwidth as well as each server's CPU capacity. Next, we devise super-operator (SO) that load balances multi-degree operator replicas. Moreover, for improving the fault-tolerance of the system, we color the SOs based on a coloring bin-packing (CBP) model that assigns peer operator replicas to different servers. To minimize the effects of input rate bursts upon the system, we take advantage of a load shedding method while keeping the QoS guarantees made by the system based on the SO scheme and the CBP model. Finally, we substantiate the utility of our work through experiments on ns-3.

Switched parasitic capacitors of sleep blocks with a tri-mode power gating structure are implemented to reduce on-chip resonant supply noise in 1.2 V, 65 nm standard CMOS process. The tri-mode power gating structure makes it possible to store charge into the parasitic capacitance of the power gated blocks. The proposed method achieves 53.1% and 57.9% noise reduction for wake-up noise and 130 MHz periodic supply noise, respectively. It also realizes noise cancelling without discharging time before using parasitic capacitors of sleep blocks, and shows 8.4x boost of the effective capacitance value with 2.1% chip area overhead. The proposed method can save the chip area for reducing resonant supply noise more effectively.

This work studies the benefits of heterogeneous cellular networks with overlapping picocells in a large macrocell. We consider three different strategies for resource allocation and cell association. The first model employs a spectrum overlapping strategy with an SINR-based cell association. The second model avoids the interference between macrocell and picocell through a spectrum splitting strategy. Furthermore, picocell range expansion is also considered in this strategy to enable a load balancing between the macrocell and picocells. The last model is a hybrid one, called as fractional spectrum splitting strategy, where spectrum splitting strategy is only applied at the picocell-edge, while the picocell-inner reuses the spectrum of the macrocell. We constructs resource allocation optimization problem for these strategies to maximize the system rate. Our results show that in terms of system rate, all the three strategies outperform the performance of macrocell-only case, which shows the benefit of heterogeneous networks. Moreover, fractional spectrum splitting strategy provides highest system rate at the expense of outage user rate degradation due to inter-macro-pico interference. Spectrum overlapping model provides the second highest system rate gain and also improves outage user rate owing to full spectrum reuse and the benefit of macro diversity, while spectrum splitting model achieves a moderate system rate gain.

One important issue in cognitive transmission is for multiple secondary users to dynamically acquire spare spectrum from the single primary user. The existing spectrum sharing scheme adopts a deterministic Cournot game to formulate this problem, of which the solution is the Nash equilibrium. This formulation is based on two implicit assumptions. First, each secondary user is willing to fully exchange transmission parameters with all others and hence knows their complete information. Second, the unused spectrum of the primary user for spectrum sharing is always larger than the total frequency demand of all secondary users at the Nash equilibrium. However, both assumptions may not be true in general. To remedy this, the present paper considers a more realistic assumption of incomplete information, i.e., each secondary user may choose to conceal their private information for achieving higher transmission benefit. Following this assumption and given that the unused bandwidth of the primary user is large enough, we adopt a probabilistic Cournot game to formulate an opportunistic spectrum sharing scheme for maximizing the total benefit of all secondary users. Bayesian equilibrium is considered as the solution of this game. Moreover, we prove that a secondary user can improve their expected benefit by actively hiding its transmission parameters and increasing their variance. On the other hand, when the unused spectrum of the primary user is smaller than the maximal total frequency demand of all secondary users at the Bayesian equilibrium, we formulate a constrained optimization problem for the primary user to maximize its profit in spectrum sharing and revise the proposed spectrum sharing scheme to solve this problem heuristically. This provides a unified approach to overcome the aforementioned two limitations of the existing spectrum sharing scheme.