We present area- and power-efficient pipeline 128- and 128/64-point fast Fourier transform (FFT) processors for 8x8 multiple-input multiple-output orthogonal frequency multiplexing (MIMO-OFDM) systems based on the specification framework of IEEE 802.11ac WLANs. Our new FFT processors use mixed-radix multipath delay commutator (MRMDC) architecture from the point of view of low complexity and high memory use. A conventional MRMDC architecture induces large circuits in delay commutators, which change the order of data sequences for the butterfly units. The proposed architecture replaces delay elements with new commutators that cooperate with other MIMO-OFDM processing blocks. These commutators are inserted in the front and rear of the input and output memory units. Our FFT processors exhibit a 50–51% reduction in logic gates and 70–72% reduction in power dissipation as compared with conventional ones.

Efficient silicon-based light sources are expected to be key devices for applications such as optical interconnection. Huge number of researches has been conducted for realizing silicon-based light sources. Most of them utilized silicon-related materials such as silicon nanostructures or germanium, not crystalline silicon, which has been considered as a poor light emitter because of its indirect electronic bandgap. Light emission properties of materials can be tailored not only by modifying the material properties directly, but also by controlling the electromagnetic environment surrounding the material. Photonic nanostructures are a powerful tool for creating the engineered environment. In this paper, we briefly review the mechanisms for improving the light emission properties of materials by photonic nanostructures and present our recent experimental results showing the enhancement of light emission from silicon by introducing photonic crystal structures.

A compact and wide stopband low-pass filter (LPF) which consists of a hairpin structural resonator, a chip-capacitor, and inductor lines is proposed in this paper. With the capacitor loaded, the hairpin structure realized three transmission zeros in the stopband. The LPF with one hairpin unit was designed using the conventional prototype design procedure in the passband. To further improve the stopband characteristics, the LPF with three hairpin units was studied and designed with the same manner as in a one unit LPF. The finally designed three-hairpin LPF showed mostly 60 dB rejection characteristics in the conjunction with defected ground condition for avoiding the spurious response at the stopband. The measurement results agreed well with simulated ones.

This paper presents two CMOS power amplifiers which realize frequency band selection. Each PA consists of two stages and uses a transformer to obtain large output power with high efficiency. Furthermore, the capacitive cross-coupling at the second stage reduces a die area of the bypass capacitance. The proposed PAs are fabricated by a 0.18 µm CMOS process. With a 3.3 V supply, the PAs achieve a output 1-dB compression point of larger than 25 dBm from 2.2 GHz to 5.4 GHz, maximum of peak power added efficiency (PAEpeak) are 30% and 27% for 2-band and 3-band PAs, respectively. The proposed PAs have advantages which are a band-selectable ability within a desired frequency range and a realization of CMOS PA with high power efficiency.

We propose a built-in planar lens for coupling light to a waveguide on a 2-D photonic crystal (PhC) membrane. A 2-D PhC waveguide with the built-in lens has been fabricated with AlGaAs. Improvement in coupling performance is discussed in comparison to waveguides with straight ends as cleaved.

An AdaBoost-based face detection system is proposed, on a Coarse Grain Reconfigurable Architecture (CGRA) named “REMUS-II”. Our work is quite distinguished from previous ones in three aspects. First, a new hardware-software partition method is proposed and the whole face detection system is divided into several parallel tasks implemented on two Reconfigurable Processing Units (RPU) and one micro Processors Unit (µPU) according to their relationships. These tasks communicate with each other by a mailbox mechanism. Second, a strong classifier is treated as a smallest phase of the detection system, and every phase needs to be executed by these tasks in order. A phase of Haar classifier is dynamically mapped onto a Reconfigurable Cell Array (RCA) only when needed, and it's quite different from traditional Field Programmable Gate Array (FPGA) methods in which all the classifiers are fabricated statically. Third, optimized data and configuration word pre-fetch mechanisms are employed to improve the whole system performance. Implementation results show that our approach under 200 MHz clock rate can process up-to 17 frames per second on VGA size images, and the detection rate is over 95%. Our system consumes 194 mW, and the die size of fabricated chip is 23 mm2 using TSMC 65 nm standard cell based technology. To the best of our knowledge, this work is the first implementation of the cascade Haar classifier algorithm on a dynamically CGRA platform presented in the literature.

To improve simulation precision, the signal model of navigation satellite signal simulators is illustrated, and the generation mechanism and evaluation criteria of an important error source-phase jitter in baseband signal generation, are studied subsequently. An improved baseband signal generator based on dual-ROM look-up table structure is designed with the application of a newly-established concept-virtual sampling rate. Pre-storage of typical baseband signal data and sampling rate conversion adaptive to Doppler frequency shifts are adopted to achieve the high-precision simulation of baseband signals. Performance analysis of the proposed baseband signal generator demonstrates that it can successfully suppress phase jitter and has better spectral performance, generating high-precision baseband signals, which paves the way to improving the overall precision of navigation satellite signal simulators.

Monolithic integration of various kinds of optical components on a silicon wafer is the key to making silicon (Si) photonics practical technology. Applying silicon photonics to telecommunications further requires low insertion loss and polarization independence. We propose an integration concept for telecommunications based on Si and related materials and demonstrate monolithic integration of passive and dynamic functional components. This article shows the great potential of Si photonics technology for telecommunications.

The explosive growth of Internet usage has caused problems for the current Internet in terms of traffic congestion within networks and performance degradation of end-to-end flows. Therefore, a reconsideration of the current Internet has begun and is being actively discussed worldwide with the goals of enabling efficient share of limited network resources (i.e., the link bandwidth) and improved performance. To directly address the inefficiency of TCP's congestion mitigation solely on the end-to-end basis, in this paper we propose an adaptive split connection scheme on advanced relay nodes; this scheme dynamically splits end-to-end TCP connections on the basis of congestion status in output links. Through simulation evaluations, we examine the effectiveness and potential of the proposed scheme.

The charge-redistribution low-swing differential logic (CLDL) circuits are presented in this work. It can implement a complex function in a single gate. The CLDL circuits utilizes the charge-redistribution and reduced-swing schemes to reduce the power dissipation and enhance the operation speed. In addition, a pipeline structure is formed by a series connection structure controlled by a true-single-phase clock, thereby achieving high-speed operation. The CLDL circuits perform more than 25% speedup and 31% in power-delay product compared to other differential circuits with true-single-phase clock. A pipelined multiplier-accumulator (MAC) using CLDL structure is fabricated in 0.35 µm single-poly four-metal CMOS process. The test chip is successfully verified to operate at 900-MHz.

Phase structure of nonlinear dynamical system is governed by the vector field and decides the trajectories. Accordingly, the power spectra of trajectories include the structural field effect on the phase space. In this paper, we develop a method for analyzing phase structure using power spectra of trajectories and reconstitute a potential function in the system.

This paper proposes Direct Spectrum Division Transmission with spectrum editing technique. The transmitter divides the single carrier modulated signal into multiple “sub-spectra” in the frequency domain and arranges each sub-spectrum so as to more fully utilize the unused frequency resources. In the receiver, the divided sub-spectra are combined in the frequency domain and demodulated. By editing the divided spectrum in the frequency domain, the total bandwidth occupied by the multiple “sub-spectra” is less than that of the modulated signal. The proposed technique allows the unused frequency resources scattered across the bands to be better utilized. Simulations show that the proposed technique makes the bit error rate negligible.

This paper proposes a method of designing EM absorber panels under oblique incident waves. TM and TE wave reflection characteristics of the absorber panel show its anisotropy under oblique incidence. By using the wire array sheet proposed this paper, TM and TE reflection coefficients in oblique incidence can be matched at almost the same frequency range.

The peer-assisted streaming paradigm has been widely employed to distribute live video data on the internet recently. In general, the mesh-based pull approach is more robust and efficient than the tree-based push approach. However, pull protocol brings about longer streaming delay, which is caused by the handshaking process of advertising buffer map message, sending request message and scheduling of the data block. In this paper, we propose a new approach, mesh-push, to address this issue. Different from the traditional pull approach, mesh-push implements block scheduling algorithm at sender side, where the block transmission is initiated by the sender rather than by the receiver. We first formulate the optimal upload bandwidth utilization problem, then present the mesh-push approach, in which a token protocol is designed to avoid block redundancy; a min-cost flow model is employed to derive the optimal scheduling for the push peer; and a push peer selection algorithm is introduced to reduce control overhead. Finally, we evaluate mesh-push through simulation, the results of which show mesh-push outperforms the pull scheduling in streaming delay, and achieves comparable delivery ratio at the same time.

Because of numerous circuit resources of FPGAs, there is a performance gap between FPGAs and ASICs. In this paper, we propose a small-memory logic cell, COGRE, to reduce the FPGA area. Our approach is to investigate the appearance ratio of the logic functions in a circuit implementation. Moreover, we group the logic functions on the basis of the NPN-equivalence class. The results of our investigation show that only small portions of the NPN-equivalence class can cover large portions of the logic functions used to implement circuits. Further, we found that NPN-equivalence classes with a high appearance ratio can be implemented by using a small number of AND gates, OR gates, and NOT gates. On the basis of this analysis, we develop COGRE architectures composed of several NAND gates and programmable inverters. The experimental results show that the logic area of 4-COGRE is smaller than that of 4-LUT and 5-LUT by approximately 35.79% and 54.70%, respectively. The logic area of 8-COGRE is 75.19% less than that of 8-LUT. Further, the total number of configuration memory bits of 4-COGRE is 8.26% less than the number of configuration memory bits of 4-LUT. The total number of configuration memory bits of 8-COGRE is 68.27% less than the number of configuration memory bits of 8-LUT.

For Doppler parameter estimation of forward-looking SAR, the third-order Doppler parameter can not be neglected. In this paper, the azimuth signal of the transmitter fixed bistatic forward-looking SAR is modeled as a cubic polynomial phase signal (CPPS) and multiple time-overlapped CPPSs, and the modified cubic phase function is presented to estimate the third-order Doppler parameter. By combining the cubic phase function (CPF) with Radon transform, the method can give an accurate estimation of the third-order Doppler parameter. Simulations validate the effectiveness of the algorithm.

In this letter, we propose an antenna selection single frequency network precoding (AS-SFNP) scheme for downlink cooperative multiple-input multiple-output (MIMO) systems, which efficiently improves system capacity with low feedback overhead and low complexity.