This paper considers the discrete model of the cart-pendulum system modeled by discrete mechanics, which is known as a good discretizing method for mechanical systems and has not been really applied to control theory. We first sum up basic concepts on discrete mechanics and discuss the explicitness of the linear approximation of the discrete Euler-Lagrange Equations. Next, the discrete cart-pendulum system is derived and analyzed from the viewpoint of solvability of implicit nonlinear control systems. We then show a control algorithm to stabilize the discrete cart-pendulum based on the discrete-time optimal regulator theory. Finally, some simulations are shown to demonstrate the effectiveness of the proposed algorithm.

In this paper, a new Hammerstein predistorter modeling for power amplifier (PA) linearization is proposed. The key feature of the model is that the cubic splines, instead of conventional high-order polynomials, are utilized as the static nonlinearities due to the fact that the splines are able to represent hard nonlinearities accurately and circumvent the numerical instability problem simultaneously. Furthermore, according to the amplifier's AM/AM and AM/PM characteristics, real-valued cubic spline functions are utilized to compensate the nonlinear distortion of the amplifier and the following finite impulse response (FIR) filters are utilized to eliminate the memory effects of the amplifier. In addition, the identification algorithm of the Hammerstein predistorter is discussed. The predistorter is implemented on the indirect learning architecture, and the separable nonlinear least squares (SNLS) Levenberg-Marquardt algorithm is adopted for the sake that the separation method reduces the dimension of the nonlinear search space and thus greatly simplifies the identification procedure. However, the convergence performance of the iterative SNLS algorithm is sensitive to the initial estimation. Therefore an effective normalization strategy is presented to solve this problem. Simulation experiments were carried out on a single-carrier WCDMA signal. Results show that compared to the conventional polynomial predistorters, the proposed Hammerstein predistorter has a higher linearization performance when the PA is near saturation and has a comparable linearization performance when the PA is mildly nonlinear. Furthermore, the proposed predistorter is numerically more stable in all input back-off cases. The results also demonstrate the validity of the convergence scheme.

We implement one-out-of-two bit oblivious transfer (OT) based on the assumptions used in the McEliece cryptosystem: the hardness of decoding random binary linear codes, and the difficulty of distinguishing a permuted generating matrix of Goppa codes from a random matrix. To our knowledge this is the first OT reduction to these problems only. We present two different constructions for oblivious transfer, one based on cut-and-chose arguments and another one which is based on a novel generalization of Bennett-Rudich commitments which may be of independent interest. Finally, we also present a variant of our protocol which is based on the Niederreiter cryptosystem.

This letter focuses on the design of selective receivers for homogeneous scenarios where a very small number of secondary data are available. To this end, at the design stage it is assumed that the cell under test (CUT) contains a fictitious signal orthogonal to the nominal steering vector under the null hypothesis; the clutter covariance matrix is modeled as a random matrix with an inverse complex Wishart distribution. Under the above assumptions, we devise two Bayesian detectors based on the GLRT criterion, both one-step and two-step. It is shown that the proposed detectors have the same detection structure as their non-Bayesian counterparts, substituting the colored diagonal sample covariance matrix (SCM) for the classic one. Finally, a performance assessment, conducted by Monte Carlo simulations, has shown that our detectors ensure better rejection capabilities of mismatched signals than the existing Bayesian detectors, at the price of a certain loss in terms of detection of matched signals.

In this letter, an area-efficient architecture for the hardware implementation of the real-time prime factor Fourier transform (PFFT) is presented. In the proposed architecture, a prime length DFT module with the one-point-per-cycle (OPPC) property is implemented by the parallel distributed arithmetic (DA), and a cyclic convolution feature is exploited to simplify the structure of the DA cells. Based on the proposed architecture, a real-time 65-point PFFT processor is designed, and the synthesis results show that it saves over 8% gates compared to the existing real-time 64-point DFT designs.

The wear leveling is a critical factor which significantly impacts the lifetime and the performance of flash storage systems. To extend lifespan and reduce memory requirements, this paper proposed an efficient wear leveling without substantially increasing overhead and without modifying Flash Translation Layer (FTL) for huge-capacity flash storage systems, which is based on selective replacement. Experimental results show that our design levels the wear of different physical blocks with limited system overhead compared with previous algorithms.

In this paper, we propose a placement and routing method for a new memory-based programmable logic device (MPLD) and confirm its capability by placing and routing benchmark circuits. An MPLD consists of multiple-output look-up tables (MLUTs) that can be used as logic and/or routing elements, whereas field programmable gate arrays (FPGAs) consist of LUTs (logic elements) and switch blocks (routing elements). MPLDs contain logic circuits more efficiently than FPGAs because of their flexibility and area efficiency. However, directly applying the existing placement and routing algorithms of FPGAs to MPLDs overcrowds the placed logic cells and causes a shortage of routing domains between logic cells. Our simulated annealing-based method considers the detailed wire congestion and nearness between logic cells based on the cost function and reserves the area for routing. In the experiments, our method reduced wire congestion and successfully placed and routed 27 out of 31 circuits, 13 of which could not be placed or routed using the versatile place and route tool (VPR), a well-known method for FPGAs.

It becomes so important to observe a wild life for obtaining not only knowledge of its biological behaviors but also interactions with human beings in terms of geoenvironmental investigation and assessment. A sensor network is considered to be a suitable and powerful tool to monitor and observe a wild life in fields. In order to monitor/observe seabirds, a sensor network is deployed in Awashima island, Japan. A sensor platform is useful for early and quick deployment in fields. Atlas, a server-client type sensor platform, is used with several sensors, i.e., infrared sensors, thermometers within a nest and a sound sensor. The experimental results and the first outcome of observation have been reported. Particularly emphasized is that an infrared sensor has detected a leaving and returning of seabirds, and has identified that a leaving and returning is affected by sunrises and sunsets. An infrared sensed data has also shown a chick's practice before flying to the south. These facts and knowledge have not been clearly obtained by observation of human beings, so have demonstrated the usefulness of sensor networking for ecology observations.

This article introduces some improvements to the already proposed custom instruction candidates selection for the automatic ISA customisation problem targeting reconfigurable processors. It introduces new opportunities to prune the search space, and a technique based on dynamic programming to check the independence between groups. The proposed new algorithm yields one order less measured number of convexity checks than the related work for the same inputs and outputs.

Generally, a programmable LSI such as an FPGA is difficult to test compared to an ASIC. There are two major reasons for this. The first is that an automatic test pattern generator (ATPG) cannot be used because of the programmability of the FPGA. The other reason is that the FPGA architecture is very complex. In this paper, we propose a new FPGA architecture that will simplify the testing of the device. The base of our architecture is general island-style FPGA architecture, but it consists of a few types of circuit blocks and orderly wire connections. This paper also presents efficient test configurations for our proposed architecture. We evaluated our architecture and test configurations using a prototype chip. As a result, the chip was fully tested using our configurations in a short test time. Moreover, our architecture can provide comparable performance to a conventional FPGA architecture.

This paper presents a method for comparing and detecting clones of Java programs by analyzing program stack flows. A stack flow denotes an operational behavior of a program by describing individual instructions and stack movements for performing specific operations. We analyze stack flows by simulating the operand stack movements during execution of a Java program. Two programs for detection of clones of Java programs are compared by matching similar pairs of stack flows in the programs. Experiments were performed on the proposed method and compared with the earlier approaches of comparing Java programs, the Tamada, k-gram, and stack pattern based methods. Their performance was evaluated with real-world Java programs in several categories collected from the Internet. The experimental results show that the proposed method is more effective than earlier methods of comparing and detecting clones of Java programs.

In this paper, the charge pump efficiency is discussed, and a dual charge pump circuit with complementary architecture using charge sharing clock scheme is presented. The proposed charge sharing clock generator is able to recover the charge from parasitic-capacitor charging and discharging, so that the dynamic power loss in the pumping process is reduced by a half. To preserve the overlapping period of the four-phase clock used for threshold cancellation technique, two complementary sets of clocks are generated from the proposed clock generator, and each set feeds a certain branch of the dual charge pump to achieve the between-branch charge sharing. A test chip is fabricated in 0.18 µm process, and the area penalty of the proposed charge sharing clock generator is 1%. From the measurement results, the proposed charge pump shows an overall power efficiency increase with a peak value of 63.7% comparing to 52.3% of a conventional single charge pump without charge sharing, and the proposed clock scheme shows no degradation on the driving capability while the output ripple voltage is reduced by 43%.

In this paper a novel and effective two phase admission control (TPAC) for QoS mobile ad hoc networks is proposed that satisfies the real-time traffic requirements in mobile ad hoc networks. With a limited amount of extra overhead, TPAC can avoid network congestions by a simple and precise admission control which blocks most of the overloading flow-requests in the route discovery process. When compared with previous QoS routing schemes such as QoS-aware routing protocol and CACP protocols, it is shown from system simulations that the proposed scheme can increase the system throughput and reduce both the dropping rate and the end-to-end delay. Therefore, TPAC is surely an effective QoS-guarantee protocol to provide for real-time traffic.

In orthogonal frequency division multiple access (OFD-MA) uplink, the distortions introduced by both multiple carrier frequency offsets (CFOs) and in-phase and quadrature-phase (IQ) imbalances will severely degrade the system performance. With both CFOs and IQ imbalances, signal detection at the receiver becomes hard, if not impossible. In this letter, a linear receiver is proposed to cope with the distortions at a slight drop in system transmission rate. The analysis and simulations demonstrate the effectiveness of the proposed approach.

In this paper a programmable and area-efficient decoder architecture supporting two decoding algorithms for Block-LDPC codes is presented. The novel decoder can be configured to decode in either TPMP or TDMP decoding mode according to different Block-LDPC codes, essentially combining the advantages of two decoding algorithms. With a regular and scalable data-path, a Reconfigurable Serial Processing Engine (RSPE) is proposed to achieve area efficiency. To verify our proposed architecture, a flexible LDPC decoder fully compliant to IEEE 802.16e applications is implemented on a 130 nm 1P8M CMOS technology with a total area of 6.3 mm2 and maximum operating frequency of 250 MHz. The chip dissipates 592 mW when operates at 250 MHz frequency and 1.2 V supply.

Existing query tree protocols deal with RFID tags in a blind manner. They query tags in a fixed bit order based on the assumption that the tag ID numbers are uniformly distributed throughout the range of the entire ID space because readers have no prior knowledge of the tags. This paper attempts to distinguish RFID applications where readers are already aware of all tags used by the application. We propose a heuristic query tree (H-QT) protocol that uses heuristic to select effective bits from known tags for the best queries in a divide and conquer approach. The performance evaluation shows that the proposed protocol is superior to original query tree protocols because it significantly reduces the number of tag collisions and no tag response.

This paper addresses stereo matching under scenarios of smooth region and obviously slant plane. We explore the flexible handling of color disparity, spatial relation and the reliability of matching pixels in support windows. Building upon these key ingredients, a robust stereo matching algorithm using local plane fitting by Confidence-based Support Window (CSW) is presented. For each CSW, only these pixels with high confidence are employed to estimate optimal disparity plane. Considering that RANSAC has shown to be robust in suppressing the disturbance resulting from outliers, we employ it to solve local plane fitting problem. Compared with the state of the art local methods in the computer vision community, our approach achieves the better performance and time efficiency on the Middlebury benchmark.

In this letter, we propose an adaptive sensing/transmission scheduling policy in which the secondary user senses the spectrum when its channel condition is poor for transmission. The adaptive sensing/transmission scheduling is modeled as a Markov process and a near-optimal algorithm is proposed to determine the sensing/transmission policy. Simulation results verify our analysis and demonstrate the superiority of the proposed algorithm.

In order to implement multidimensional scaling (MDS) efficiently, we propose a new method named “global mapping analysis” (GMA), which applies stochastic approximation to minimizing MDS criteria. GMA can solve MDS more efficiently in both the linear case (classical MDS) and non-linear one (e.g., ALSCAL) if only the MDS criteria are polynomial. GMA separates the polynomial criteria into the local factors and the global ones. Because the global factors need to be calculated only once in each iteration, GMA is of linear order in the number of objects. Numerical experiments on artificial data verify the efficiency of GMA. It is also shown that GMA can find out various interesting structures from massive document collections.

In this paper, we introduce a generalized minimum mean-square error short-time spectral amplitude estimator with a new prior estimation of the speech probability density function based on moment-cumulant transformation. From the objective and subjective evaluation experiments, we show the improved noise reduction performance of the proposed method.