In this paper, we propose a 1-cycle high-performance 3D bufferless router with a 3-stage permutation network. The proposed router utilizes the 3-stage permutation network instead of the serialized switch allocator and 77 crossbar to achieve the frequency of 1.25 GHz in TSMC 65 nm technology. Compared with the other two 3D bufferless routers, the proposed router occupies less area and consumes less power consumption. Simulation results under both synthetic and application workloads illustrate that the proposed router achieves less average packet latency than the other two 3D bufferless routers.

In this study, a precoding scheme based on QR-decomposition is proposed for mitigating the inter-carrier-interference (ICI) in orthogonal-frequency-division-multiplexing (OFDM) systems. The proposed approach first subjects the ICI matrix to QR decomposition so that the ICI effect is transformed into its spectrally causal equivalent. With this causality, the precoding can then be conducted based on the resultant spectrally causal matrix. In addition, by using the stationary property of the ICI factors, in conjunction with zero padding, we implement the QR-based precoding in a segmentation manner which can significantly alleviate the computational complexity imposed by QR decomposition while eliminating ICI within each segment. This study also analyzes the residue interference power induced by the segmentation. The residue interference power is then accordingly used to determine the order of zero padding. Computer simulations support the validity of the proposed approach.

Recently, the 3-D vertical Floating Gate (FG) type NAND cell arrays with the Sidewall Control Gate (SCG), such as ESCG, DC-SF and S-SCG, are receiving attention to overcome the reliability issues of Charge Trap (CT) type device. Using this novel cell structure, highly reliable flash cell operations were successfully implemented without interference effect on the FG type cell. However, the 3-D vertical FG type cell has large cell size by about 60% for the cylindrical FG structure. In this point of view, we intensively investigate the scalability of the FG width of the 3-D vertical FG NAND cells. In case of the planar FG type NAND cell, the FG height cannot be scaled down due to the necessity of obtaining sufficient coupling ratio and high program speed. In contrast, for the 3-D vertical FG NAND with SCG, the FG is formed cylindrically, which is fully covered with surrounded CG, and very high CG coupling ratio can be achieved. As results, the scaling of FG width of the 3-D vertical FG NAND cell with S-SCG can be successfully demonstrated at 10 nm regime, which is almost the same as the CT layer of recent BE-SONOS NAND.

Applying Distributed Video Coding (DVC) to mobile devices that have limited computation and power resources can be a very challenging problem due to its high-complexity decoding. To address this, this paper proposes a DVC bitstream organizer. The proposed DVC bitstream organizer reduces the complexity associated with repetitive channel decoding and SI generation in a flexible manner. It allows users to choose a means of minimizing the computational complexity of the DVC decoder according to their preferences and the device's resource limitations. An experiment shows that the proposed method increases decoding speeds by up to 25 times.

The performances of the conventional planar type 1T DRAM and the Vertical type 1T DRAM are compared based on structure difference using a fully-consistent device simulator. We discuss the structural advantage of the Vertical type 1T-DRAM in comparison with the conventional planar type 1T-DRAM, and evaluate their performance in each operating mode such as write, erase, read, and hold; and discuss its cell performances such as Cell Current Margin and data retention. These results provide a useful guideline designing the high performance Vertical type 1T-DRAM cell.

With the purpose of improving the performance of next generation wireless networks, cooperative relaying (CoR) and network coding (NC) are promising techniques. The number of time slots required for NC in bidirectional transmission is less than that required for CoR, and hence, NC can achieve higher throughput performance than CoR. However, the disadvantage of NC is that asymmetric traffic ratio conditions might cause a significant decrease in the bidirectional throughput. In contrast, CoR is robust to asymmetric traffic ratio conditions. In this paper, in order to improve the throughput of NC even under asymmetric traffic ratio conditions, we propose an opportunistic scheduling scheme for hybrid NC and CoR. In the proposed scheduling scheme, the transmission protocol with best throughput performance can be adaptively selected based on instantaneous channel state information. Computer simulation results reveal that the proposed scheduling scheme not only achieve higher throughput than the conventional scheduling scheme but is also robust against asymmetric traffic ratio conditions. By adjusting the scheduler's parameter, the proposed scheduling scheme can provide a tradeoff between the throughput and the traffic ratio. Moreover, in certain cases, maximizing the throughput of NC and guaranteeing the offered traffic ratio can be achieved at the same time.

As an add-on device option for the ultra-low power CMOS technology, the double-gated vertical-channel Tunnel Field-Effect Transistors (TFETs) of different source configurations are comparatively studied from the perspectives of fabrication and current drivability. While the top-source design where the source of the device is placed on the top of the fin makes the fabrication and source engineering much easier, it is more susceptible to parasitic resistance issue. The bottom-source design is difficult to engineer the tunneling barrier and may require a special replacement technique. Examples of the schemes to engineer the tunneling barrier for the bottom-source TFET are suggested. A TCAD simulation study on the bottom-source devices shows that both the parasitic resistance of source region and the current enhancement mechanism by field coupling need be carefully considered in designing the source.

Cognitive radios are intelligent communications, and are expected to more efficiently utilize the radio channel. Modulation identification is one of the key issues in the cognitive radios. Many works were devoted to the classification of symbol-by-symbol modulations, however, few papers on block modulations have been published. In this paper, an identification error analysis is presented for block orthogonal modulations using General Orthogonal Modulation~(GOM). A symbol error probability is derived for the identified block orthogonal modulation. Numerical results of 4-dimensional block orthogonal modulation are presented with simulation results.

In this letter, we propose a novel resource allocation scheme to enhance downlink system performance for orthogonal frequency division multiple access (OFDMA) and time division duplex (TDD) based femtocell networks. In the proposed scheme, the macro base station (mBS) and femto base stations (fBSs) service macro user equipments (mUEs) and femto user equipments (fUEs) in inner and outer zones in different periods to reduce interference substantially. Simulations show the proposed scheme outperforms femtocell networks with fractional frequency reuse (FFR) systems in terms of the system capacity and outage probability for mUEs and fUEs.

In order to improve the address discharge characteristics, we propose the modified selective reset waveform utilizing the address-bias voltage (Va-bias) during the ramp-up period. It is revealed that the proper Va-bias makes the weak discharge between the address and scan electrodes which plays a role in sufficiently removing the wall charge, thereby contributing to minimizing the wall-voltage variation during the address-period. As a result of adopting the Va-bias in the conventional selective reset driving waveform, it was found that the address discharge delay time can be shortened by approximately 40 ns and the address period of each subfield can be significantly reduced by about 43 µs.

In this paper, we propose an interleaving updating framework of disparity and confidence map (IUFDCM) for stereo matching to eliminate the redundant and interfere information from unreliable pixels. Compared with other propagation algorithms using matching cost as messages, IUFDCM updates the disparity map and the confidence map in an interleaving manner instead. Based on the Confidence-based Support Window (CSW), disparity map is updated adaptively to alleviate the effect of input parameters. The reassignment for unreliable pixels with larger probability keeps ground truth depending on reliable messages. Consequently, the confidence map is updated according to the previous disparity map and the left-right consistency. The top ranks on Middlebury benchmark corresponding to different error thresholds demonstrate that our algorithm is competitive with the best stereo matching algorithms at present.

Clickstreams in users' navigation logs have various data which are related to users' web surfing. Those are visit counts, stay times, product types, etc. When we observe these data, we can divide clickstreams into sub-clickstreams so that the pages in a sub-clickstream share more contexts with each other than with the pages in other sub-clickstreams. In this paper, we propose a method which extracts more informative rules from clickstreams for web page recommendation based on genetic programming and association rules. First, we split clickstreams into sub-clickstreams by contexts for generating more informative rules. In order to split clickstreams in consideration of context, we extract six features from users' navigation logs. A set of split rules is generated by combining those features through genetic programming, and then informative rules for recommendation are extracted with the association rule mining algorithm. Through experiments, we verify that the proposed method is more effective than the other methods in various conditions.

In this paper, a 60 nm-thick ferroelectric film of poly(vinylidene fluoride–trifluoroethylene) on a flexible substrate of aluminum foil was fabricated and characterized. Compared to pristine silicon wafer, Al-foil has very large root-mean-square (RMS) roughness, thus presenting challenges for the fabrication of flat and uniform electronic devices on such a rough substrate. In particular, RMS roughness affects the leakage current of dielectrics, the uniformity of devices, and the switching time in ferroelectrics. To avoid these kinds of problems, a new thin film fabrication method adopting a detach-and-transfer technique has been developed. Here, 'detach' means that the ferroelectric film is detached from a flat substrate (sacrificial substrate), and 'transfer' refers to the process of the detached film being moved onto the rough substrate (main substrate). To characterize the dielectric property of the transferred film, polarization and voltage relationships were measured, and the results showed that a hysteresis loop could be obtained with low leakage current.

We propose a new three-dimensional (3D) NAND flash memory array having Tied Bit-line and Ground Select Transistor (TiGer) [1]. Channels are stacked in the vertical direction to increase the memory density without the device size scaling. To distinguish stacked channels, a novel operation scheme is introduced instead of adding supplementary control gates. The stacked layers are selected by using ground select line (GSL) and common source line (CSL). Device structure and fabrication process are described. Operation scheme and simulation results for program inhibition are also discussed.

In this paper, a Schmitt Trigger based 10T SRAM (ST 10T SRAM) cell with the vertical MOSFET is proposed for low supply voltage operation, and its impacts on cell size, stability and speed performance are investigated. The proposed ST 10T SRAM cell with the vertical MOSFET achieves smaller cell size than the ST 10T SRAM cell with the conventional planar MOSFET. Moreover, the proposed SRAM cell realizes large and constant static noise margin (SNM) against bottom node resistance of the vertical MOSFET without any architectural changes from the present 6T SRAM architecture. The proposed SRAM cell also suppresses the degradation of the read time of the ST 10T SRAM cell due to the back-bias effect free characteristic of the vertical MOSFET. The proposed ST 10T SRAM cell with the vertical MOSFET is a superior SRAM cell for low supply voltage operation with a small cell size, stable operation, and fast speed performance with the present 6T SRAM architecture.

In this work we propose a novel smart card based privacy-protecting authentication scheme for roaming services. Our proposal achieves so-called Class 2 privacy protection, i.e., no information identifying a roaming user and also linking the user's behaviors is not revealed in a visited network. It can be used to overcome the inherent structural flaws of smart card based anonymous authentication schemes issued recently. As shown in our analysis, our scheme is computationally efficient for a mobile user.

The traffic adaptive 2-level active period control has been proposed as a traffic adaptation mechanism to handle temporal and spatial (geographical) traffic fluctuations in cluster-based wireless sensor networks (WSNs) employing IEEE802.15.4 medium access control (MAC). This paper proposes a traffic adaptive distributed backoff control mechanism for cluster-based WSNs with the traffic adaptive 2-level active period control to enhance the system performance, especially transmission performance. The proposed mechanism autonomously adjusts the starting time of the backoff procedure for channel accesses in the contention access period (CAP) specified by the IEEE802.15.4 MAC, and then distributes the channel access timing over a wide range within the CAP, which can mitigate channel access congestion. The results of computer simulations show that the proposed mechanism can improve the transmission delay performance while keeping the enhancement in throughput and energy consumption at the cluster-based WSNs under non-uniform traffic environments.

We have investigated the low-power circuit applicability of hetero-gate-dielectric tunneling field-effect transistors (HG TFETs). Based on the device-level comparison of HG, SiO2-only and high-k-only TFETs, their circuit performance and energy consumption have been discussed. It has been shown that HG TFETs can deliver 14400x higher performance than the SiO2-only TFETs and 17x higher performance than the high-k-only TFETs due to its higher on current and lower capacitance at the same static power, same power supply. It has been revealed that HG TFETs have better voltage scalability than the others. It is because HG TFETs dissipate only 8% of energy consumption of SiO2-only TFETs and 17% of that of high-k-only TFETs under the same performance condition.

By performing the encoding operation on several message packets, rateless coding in cooperative networks has the potential risk of processing information already available to the receivers. In this paper, the intermediate packet decodability of rateless codes is exploited to mitigate such redundant packet processing at the cooperating nodes. The message packets that are already decoded at the receivers are eliminated from further processing by harnessing the back channel (from receiver to transmitter) for feedback. This reduces the required number of transmissions and optimizes the throughput of the network.

This paper proposes a video-quality estimation method based on a reduced-reference model for realtime quality monitoring in video streaming services. The proposed method chooses representative-luminance values for individual original-video frames at a server side and transmits those values, along with the pixel-position information of the representative-luminance values in each frame. On the basis of this information, peak signal-to-noise ratio (PSNR) values at client sides can be estimated. This enables realtime monitoring of video-quality degradation by transmission errors. Experimental results show that accurate PSNR estimation can be achieved with additional information at a low bit rate. For SDTV video sequences which are encoded at 1 to 5 Mbps, accurate PSNR estimation (correlation coefficient of 0.92 to 0.95) is achieved with small amount of additional information of 10 to 50 kbps. This enables accurate realtime quality monitoring in video streaming services without average video-quality degradation.