A C1 interpolation scheme for constructing surface patch on n-sided region (n5, 6) is presented. The constructed surface patch matches the given boundary curves and cross-boundary slopes on the sides of the n-sided region (n5, 6). This scheme has relatively simple construction, and offers one degree of freedom for adjusting interior shape of the constructed interpolation surface. The polynomial precision set of the scheme includes all the polynomials of degree three or less. The experiments for comparing the proposed scheme with two schemes proposed by Gregory and Varady respectively and also shown.

IC performance simulation for statistical purpose is usually very time-consuming since the scale and complexity of IC have increased greatly in recent years. A common approach for reduction of simulation cost is aimed at the nature of simple modeling instead of actual circuit performance simulations. In this paper,a stochastic interpolation model (SIM) scheme is proposed which overcomes the drawbacks of the existing polynomial-based approximation schemes. First,the dependence of the R2press statistic upon a parameter in SIM is taken into account and by maximizing R2press this enables SIM to achieve the best approximation accuracy in the given sample points without any assumption on the sample data. Next, a sequential sampling strategy based on variance analysis is described to effectively construct SIM during its update process. In each update step, a new sample point with a maximal value of variance is added to the former set of the sample points. The update process will be continued until the desired approximation accuracy is reached. This would eventually lead to the realization of SIM with a quite small number of sample points. Finally, the coefficient of variance is introduced as another criterion for approximation accuracy check other than the R2press statistic. The effectiveness of presented implementation scheme is demonstrated by several numerical examples as well as a statistical circuit analysis example.

This paper describes the current implementation and experimental results of a hardware/software codesign system for ASIP (Application Specific Integrated Processor) development： the PEAS-I System. The PEAS-I system accepts a set of application programs written in C language, associated data set, module database, and design constraints such as chip area and power consumption. The system then generates an optimized CPU core design in the form of an HDL as well as a set of application program development tools such as a C compiler, an assembler and a simulator. Another important feature of the PEAS-I system is that the system is able to give accurate estimations of chip area and performance before the detailed design of the ASIP is completed. According to the experimental results, the PEAS-I system has been found to be highly effective and efficient for ASIP development.

In this paper, we study a dynamic bandwidth control which is expected an effective use of network resources in transmitting highly bursty traffic generated by, e.g., interconnected LAN systems. First, a new LAN traffic model is proposed in which correlation of not only packet interarrival times but also packet lengths are considered. An analytic model for a LAN-ATM gateway is next introduced. It employs the dynamic bandwidth control using the proposed LAN traffic model and some performance measures are derived by it. The analytic model takes into account the probability that a bandwidth increase request may be rejected. Finally, some numerical examples are provided using the analysis method and performance comparisons between the dynamic and fixed bandwidth controls are made. As a result, it is quantitatively indicated that () if the equivalent bandwidth is used in average, the dynamic bandwidth control keeps packet and cell loss rates one to two orders lower than the fixed bandwidth control, () when the more strict QOS in terms of loss rate is requested, the dynamic bandwidth control can become more effective.

Dislocation-free thin silicon layers are created on the three kinds of substrates such as oxide film, synthetic quartz glass and sapphire. They are bonded with silicon wafers using hydrogen bonding at room temperature but without any adhesive, and their bonding are changed into covalent bonding at elevated temperature. Thick (2 µm) silicon layers are first produced by surface grinding and polishing, and then thinned to 0.1 µm by plasma assisted chemical etching (PACE). A multiple repeated process of thinning the silicon layer and annealing the bonded silicon/quartz and silicon/sapphire interface is applied for tight bonding between a silicon wafer and a quartz wafer, and a silicon wafer and a sapphire wafer which have different thermal expansion coefficients. In case of bonding with sapphire, oxide with 200 in thickness plays an important role in the preventions of void formation and diffusion of interface contaminants into the silicon layer.

The dielectric breakdown characteristics of a thin gate oxide during high-current ion implantation with an electron shower have been investigated by controlling the energy distribution of the electrons. Degradation of the oxide has also been discussed with regard to the total charge injected into the oxide during ion implantation in comparison with that of the TDDB (time dependent dielectric breakdown). Experimental results show that the high-energy and high-density electrons which concentrated in the circumference of the ion beam due to the space charge effect cause the degradation of the thin oxide. It was confirmed that eliminating the high-energy electrons by applying magnetic and electric fields lowers the electron energy at the wafer surface, thereby effectively suppressing the negative charge-up.

This paper proposes a buried-LATID structure featuring a peaked vertical profile around gate edge for the n- drain unlike the reported conventional LATID structure. As compared to the conventional LATID FETs, the deep-submicron buried-LATID FETs achieve improved circuit speed by 7% (50% compared to LDD FETs) due to suppressed gate-to-drain capacitance and improved lifetime by 10 times (300 times compared to LDD FETs). The buried-LATID FETs are very promising for deep-submicron MOSFETs to achieve improved performance and hot-carrier reliability at the same time.

This paper discusses a way of identifying the network configuration of ATM-LANs, which are composed of a number of ATM hubs. In general, a Network Management System (NMS) sets and gets the necessary data to and from the network elements. In managing an ATM-LAN, the ATM connection between the NMS and each network element, namely the ATM hub, must be established in order to get and set the necessary data. This forms a remarkable contrast with conventional LANs such as the IEEE802.3 LAN, which is a shared media network and enables broadcast communication without setting up any connection. This paper proposes a new protocol and a procedure that establishes the ATM connection between the NMS and each ATM hub, while identifying the overall network configuration. First, this paper makes clear the peculiarity of the ATM-LAN in terms of automatically identifying the network configuration. Next, the identification protocol that achieves the required properties is precisely explained. Then, the proposed identification protocol is evaluated in terms of required bandwidth and identification time.

This paper discusses how to provide selective broadcast communication for a group of multiple entities in a distributed system by using high-speed communication networks. In the group communication, protocol data units (PDUs) sent by each entity have to be delivered atomically in some order to all the destinations in the group. In distributed applications, each entity sends a PDU only to a subset rather than all the entities, and each entity needs to receive all the PDUs destined to it from every entity in the same order as they are sent. We name such a broadcast service a selective order-preserving broadcast (SP) service. In this paper, we discuss how to design a distributed, asynchronous protocol which provides the SP service for entities.

A 0.25-µm BiCMOS technology has been developed using three sophisticated technologies; the HSST/BiCMOS device, synchrotron orbital radiation (SOR) X-ray lithography, and an advanced two-level metallization. The HSST/BiCMOS provides a 25.4-ps double-poly bipolar device using High-performance Super Self-Aligned Process Technology (HSST), and a 42 ps/2 V CMOS inverter. SOR lithography allows a 0.18 µm gate and 0.2 µm via-hole patternings by using single-level resists. The metallization process features a new planarization technique of the 0.3-µm first wire, and a selective CVD aluminum plug for a 0.25 µm via-hole with contact resistance lower than 1Ω. These 0.25-µm technologies are used to successfully fabricate a 4 KG 0.25 µm CMOS gate-array LSI on a BiCMOS test chip of 12 mm square, which operates at 58 ps/G at 2 V. This result demonstrates that SOR lithography will pave the way for the fabrication of sub-0.25-µm BiCMOS ULSIs.

The use of computers with private networks has accelerated the electronic storage of business information in office systems. With the rapid progress in processing capability and small sizing of the computer world, private networks are going to be more intelligent. The utilization of shared information is a key issue in modern organizations, in order to increase the productivity of white-collar workers. In the CSCW research field, it is said that informal and unstructured information is important in group work contexts but difficult to locate in a large organization. Many researchers are paying particular attention to the importance of support systems for such information. These kinds of information are called Organizational memory or Group Memory. Our research focuses on knowledge propagation with private networks in the organization. This means emphasis on the process; with which organized information or the ability to use information is circulated throughout the organization. Knowledge propagation has three issues: knowledge transmission, destination locating and source locating. To cope with these issues we developed FISH, which stands for Flexible Information Sharing and Handling system. FISH was designed to provide cooperative information sharing in a group work context and to explore knowledge propagation. FISH stores fragmental information as cards with multiple keywords and content. This paper discusses a three-layered model that describes computer supported knowledge transmission. Based on this model, three issues are discussed regarding knowledge propagation. FISH and its two-year experiment are described and knowledge propagation is explored based on the results of this experiment.

Asynchronous Transfer Mode (ATM) shared buffer switches have numerous advantages, but have the principal disadvantage that all switch traffic must pass through the bottleneck of a single memory. To achieve the most efficient usage of this bottleneck, the shared buffer is made blockable, resulting in a switch architecture that we call "throttled-buffer", which has several advantageous properties. Shared buffer efficiency is maximized while decreasing both capacity and power requirements. Asynchronous operation is possible, whereby peak link data rates are allowed to approach the aggregate switch rate. Multicasting is also efficiently supported. The architecture and operation of this low-cost switch are described in detail.

There has been growing interest in Broadband ISDN (B-ISDN) based on ATM (Asynchronous Transfer Mode) technologies, since ATM is expected to support a wide range of applications through high-speed and flexible multimedia communication capabilities. This paper reviews and discusses technical issues on multimedia communication protocols and services from the integration points of view of computer and communication technologies. An ISDN-based distributed multimedia and multi-party desktop conference system called MERMAID is introduced as an example which offers highly-sophisticated functions for remote collaborations among multiple users. This system, which was developed in early 1989 and has been used for daily research work since then, involves B-ISDN key technologies related to multimedia and multicast protocols, and computer architecture for groupware applications.

This paper describes a new method to estimate traffic load of communication nodes, such as switching systems. The new method uses the system identification, which is often used in designing control systems of real systems. First, this paper makes clear that, under certain conditions, the input and output relation of a communication system, which is composed of a number of communication nodes, is formulated into a dynamic state equation that is classed as a time-invariant, single-input single-output, discrete-time system. Next, it is explained that traffic load information is estimated by identifying the dynamic state equations of the communication system. Then, the traffic load estimator is synthesized using the system identification in it. Finally, it is clarified by computation simulations that the proposed method is very applicable in estimating the traffic load of each communication node.

In this paper, an efficient and robust circuit parameter determination method suitable for analog circuit synthesis is presented. The method uses block diagram representation of circuits as implicit design knowledge. Circuit parameter determination is carried out by propagating known values along signal flow in the block diagram. The circuit parameter determination using signal propagation performs successfully when unknown circuit parameters can be solved in one way. However, when the block diagram involves implicit calculation, the propagation stops before all unknown parameters are determined. In order to cope with this problem, we introduced a method that employs a symbolic analysis technique combined with a numerical method. When the propagation of known values stops, one of unknown signals is selected, a unique symbol is assigned to the selected signal, and the signal propagation is restarted. This operation is repeated until there is no unknown signal. When the symbol propagation reaches the signal where the signal value is already set, one nonlinear equation for the signal is obtained by equating both signal values. It can be solved by a numerical method, such as Newton's method. The parameter determination method using procedural description is superior to the optimization based method because it is straightforward to incorporate design knowhow in the description. However, it is burdensome for designers to develop design procedures for each circuit to be synthesized. Because the block diagram based calculation method can be used as subroutine calls during the design procedure development, it simplifies the design procedural description and lowers the burden of designers. The method was applied to the element value determination of bias circuits to demonstrate its effectiveness.

This paper proposes new algorithms for adaptive FIR filters. The proposed algorithms provide both fast convergence and small final misadjustment with an adaptive step size even under an interference to the error. The basic algorithm pays special attention to the interference which contaminates the error. To enhance robustness to the interference, it imposes a special limit on the increment/decrement of the step-size. The limit itself is also varied according to the step-size. The basic algorithm is extended for application to nonstationary signals. Simulation results with white signals show that the final misadjustment is reduced by up to 22 dB under severe observation noise at a negligible expense of the convergence speed. An echo canceler simulation with a real speech signal exhibits its potential for a nonstationary signal.

This paper studies the problem of embedding a graph into a book with nodes on a line along the spine of the book and edges on the pages in such a way that no edge crosses another. Atneosen as well as Bernhart and Kainen has shown that every graph can be embedded into a 3-page book when each edge can be embedded in more than one page. The time complexity of Bernhart and Kainen's method is Ω(ν(G)), where ν(G) is the crossing number of a graph G. A new 0(mn) algorithm is derived in this paper for embedding a graph G=(V, E), where m=│E│ and n= │V│ . The number of points at which edges cross over the spine in embedding a complete graph into a 3-page book is also investigated.

Genetic algorithms have been shown to be very useful in a variety of search and optimization problems. In this paper, we describe the implementation of genetic algorithms for channel routing problems and identify the key points which are essential to making full use of the population of potential solutions, that is one of the characteristics of genetic algorithms. Three efficient crossover techniques which can be divided further into 13 kinds of crossover operators have been compared. We also extend our previous work with ability to deal with dogleg case by simply splitting multi-terminal nets into a series of 2-terminal subnets. It routes the Deutsch's difficult example with 21 tracks without any detours.

This paper describes a future private network service and the system configurations for providing it. Technologies and service trends in local area and wide area networks are shown. As network services become more diversified and integrated, it becomes more difficult for users to use the networks effectively. This paper shows how this problem can be solved by using virtual network technology to attain seamless networking. It also presents the concept of group networking among many parties, which can be used as the basis for a virtual private network.

Recently, efficient algorithms that exploit the separability of nonlinear mappings have been proposed for finding all solutions of piecewise-linear resistive circuits. In this letter, it is shown that these algorithms can be extended to circuits containing piecewise-linear resistors that are neither voltage nor current controlled. Using the parametric representation for these resistors, the circuits can be described by systems of nonlinear equations with separable mappings. This separability is effectively exploited in finding all solutions. A numerical example is given, and it is demonstrated that all solutions are computed very rapidly by the new algorithm.