New critical-dimension controlling technique of off-axis illumination for aperiodic patterns has been developed. By means of arranging not-imaging additional pattern near 0.25 micron isolated patterns, the depth of focus of an isolated pattern was improved as well as the periodic patterns. Simulation and experimental results were verified on a 0.48 numerical-aperture, KrF excimer laser stepper. Using new deep-ultra-violet hardening technique for chemically amplified positive resist, the critical dimension loss of resist pattern was prevented. 0.25 micron design rule pattern was obtained with excellent mask linearity without critical-dimension-loss. The combination techniques are achieved quarter micron design rule complex circuit pattern layouts.

In this paper, we study a dynamic bandwidth control which is expected an effective use of network resources in transmitting highly bursty traffic generated by, e.g., interconnected LAN systems. First, a new LAN traffic model is proposed in which correlation of not only packet interarrival times but also packet lengths are considered. An analytic model for a LAN-ATM gateway is next introduced. It employs the dynamic bandwidth control using the proposed LAN traffic model and some performance measures are derived by it. The analytic model takes into account the probability that a bandwidth increase request may be rejected. Finally, some numerical examples are provided using the analysis method and performance comparisons between the dynamic and fixed bandwidth controls are made. As a result, it is quantitatively indicated that () if the equivalent bandwidth is used in average, the dynamic bandwidth control keeps packet and cell loss rates one to two orders lower than the fixed bandwidth control, () when the more strict QOS in terms of loss rate is requested, the dynamic bandwidth control can become more effective.

A C1 interpolation scheme for constructing surface patch on n-sided region (n5, 6) is presented. The constructed surface patch matches the given boundary curves and cross-boundary slopes on the sides of the n-sided region (n5, 6). This scheme has relatively simple construction, and offers one degree of freedom for adjusting interior shape of the constructed interpolation surface. The polynomial precision set of the scheme includes all the polynomials of degree three or less. The experiments for comparing the proposed scheme with two schemes proposed by Gregory and Varady respectively and also shown.

This paper discusses a way of identifying the network configuration of ATM-LANs, which are composed of a number of ATM hubs. In general, a Network Management System (NMS) sets and gets the necessary data to and from the network elements. In managing an ATM-LAN, the ATM connection between the NMS and each network element, namely the ATM hub, must be established in order to get and set the necessary data. This forms a remarkable contrast with conventional LANs such as the IEEE802.3 LAN, which is a shared media network and enables broadcast communication without setting up any connection. This paper proposes a new protocol and a procedure that establishes the ATM connection between the NMS and each ATM hub, while identifying the overall network configuration. First, this paper makes clear the peculiarity of the ATM-LAN in terms of automatically identifying the network configuration. Next, the identification protocol that achieves the required properties is precisely explained. Then, the proposed identification protocol is evaluated in terms of required bandwidth and identification time.

There has been growing interest in Broadband ISDN (B-ISDN) based on ATM (Asynchronous Transfer Mode) technologies, since ATM is expected to support a wide range of applications through high-speed and flexible multimedia communication capabilities. This paper reviews and discusses technical issues on multimedia communication protocols and services from the integration points of view of computer and communication technologies. An ISDN-based distributed multimedia and multi-party desktop conference system called MERMAID is introduced as an example which offers highly-sophisticated functions for remote collaborations among multiple users. This system, which was developed in early 1989 and has been used for daily research work since then, involves B-ISDN key technologies related to multimedia and multicast protocols, and computer architecture for groupware applications.

Genetic algorithms have been shown to be very useful in a variety of search and optimization problems. In this paper, we describe the implementation of genetic algorithms for channel routing problems and identify the key points which are essential to making full use of the population of potential solutions, that is one of the characteristics of genetic algorithms. Three efficient crossover techniques which can be divided further into 13 kinds of crossover operators have been compared. We also extend our previous work with ability to deal with dogleg case by simply splitting multi-terminal nets into a series of 2-terminal subnets. It routes the Deutsch's difficult example with 21 tracks without any detours.

Optical and electrical measurements of thin film n-channel SOI-MOSFETs reveal that the exponential tail in photon emission spectra originates from electron-hole recombination. Bremsstrahlung radiation model as a physical mechanism of photon emission was experimentally negated. Negative threshold voltage shift at the initial stage of high field stress is found to be caused by hole trapping in buried oxide. Subsequent turnover characteristics is explained by a competing process between electron trapping in the front gate oxide and hole trapping in the buried oxide. As to the degradation of transconductance, generated surface state as well as trapped holes in the buried oxide which reduce vertical electric field in SOI film are involved in the complicate degradation of transconductance.

Upper bounds on the bit error probability and repeat request probability, and lower bounds on the throughput are derived for a Hybrid-ARQ scheme that employs trellis-coded modulation on a fading dispersive channel. The receiver employs a modified Viterbi algorithm to perform joint maximum likelihood sequence estimation (MLSE) equalization and decoding. Retransmissions are generated by using the approach suggested by Yamamoto and Itoh. The analytical bounds are extended to trellis-coded modulation on fading dispersive channels with code combining. Comparison of the analytical bounds with simulation results shows that the analytical bounds are quite loose when diversity reception is not employed. However, no other analytical bounds exist in the literature for the trellis-coded Hybrid ARQ system studied in this paper. Therefore, the results presented in this paper can provide the basis for comparison with more sophisticated analytical bounds that may be derived in the future.

For the efficient circuit simulation, several direct/relaxation-based mixed mode simulation techniques have been studied. This paper proposes the combination of selective trace, which is well-known in the logic simulation, with dynamic network separation. In the selective trace method, the time points to be analyzed are selected for each subcircuit. Since the separation technique enables the analysis of each subcircuit independently, it is possible to skip solving the latent subcircuits, according to selective trace. Selecting the time points in accordance with activity of each subcircuit is analogous to multirate numerical integration technique used in the waveform relaxation algorithm.

We have studied a circuit partitioning approach in the view of parallel circuit simulation on a MIMD parallel computer. In parallel circuit simulation, a circuit is partitioned into equally sized subcircuits while minimizing the number of interconnection nodes. Besides circuit partitioning time should be short enough compared with the total simulation time. From the details of circuit simulation time, we found that balancing subcircuits is critical for low parallel processing, whereas minimizing the interconnection nodes is critical for highly parallel processing. Our circuit partitioning approach consists of four steps： Grouping transistors, initial partitioning the transistor-groups, minimizing the number of interconnection nodes, and balancing the subcircuits. It is based on an algorithmic approach, and can directly control the tradeoffs between balancing subcircuits and minimizing the interconnection nodes by adjusting the parameters. We partitioned a test circuit with 3277 transistors into 4, 9, ... , 64 subcircuits, and did parallel simulations using PARACS, our parallel circuit simulator, on an AP1000 parallel computer. The circuit partitioning time was short enough-less than 3 percent of the total simulation time. The highest performance of parallel analysis using 49 processors was 16 times that of a single processor, and that for total simulation was 9 times.

In order to construct a high-capacity and high-reliable indoor wireless communications system, it is essential to design the modulation/demodulation, coding and access schemes with high and variable data rate transmission capabilities, which meet the technical requirements inherent to wireless communications, i.e., high frequency utilization efficiency and robustness for fading. In this paper, we propose the frequency and time division multiple access with demand-assignment (FTDMA/DA) using multicarrier modulation as a frequency and time synchronous answer to meet the requirements, and analyze the performance of the FTDMA/DA system, taking account of teletraffic characteristics of multimedia information sources.

The dielectric breakdown strength of thermally grown silicon dioxide films was studied for MOS capacitors fabricated on silicon wafers that were intentionally contaminated with magnesium and zinc. Most of magnesium was detected in the oxide film after oxidation. Zinc, some of which evaporated from the surface of wafers, was detected only in the oxide film. The mechanism of the dielectric degradation is dominated by formation of metal silicates, such as Mg2SiO4 (Forsterite) and Zn2SiO4 (Wilemite). The formation of metal silicates has no influence on the generation lifetime of minority carriers, however, it provides the flat-band voltage shift less than 0.3 eV, and forces to increase the density of deep surface states with the zinc contamination.

A method of range image segmentation using four Markov random field(MRF)s is described in this paper. MRFs are used in depth smoothing, gradient smoothing, edge detection and surface type labeling stage. First, range and its gradient images are smoothed preserving jump and roof edges respectively using line process concept one after another. Then jump and roof edges are extracted, combined and refined using penalizing undesirable edge patterns. Finally, curvatures are computed and the surface types are labeled according to the signs of principal curvatures. The surface type labels are refined using winner-takes-all layers in the stage. The final output is a set of regions with its exact surface type. The energy function is used in order to represent constraints of each stage and the minimum energy state is found using iterative method. Several experimental results show the generality of our approach and the execution speed of the proposed method is faster than that of a typical region merging method. This promises practical applications of our method.

A 0.25-µm BiCMOS technology has been developed using three sophisticated technologies; the HSST/BiCMOS device, synchrotron orbital radiation (SOR) X-ray lithography, and an advanced two-level metallization. The HSST/BiCMOS provides a 25.4-ps double-poly bipolar device using High-performance Super Self-Aligned Process Technology (HSST), and a 42 ps/2 V CMOS inverter. SOR lithography allows a 0.18 µm gate and 0.2 µm via-hole patternings by using single-level resists. The metallization process features a new planarization technique of the 0.3-µm first wire, and a selective CVD aluminum plug for a 0.25 µm via-hole with contact resistance lower than 1Ω. These 0.25-µm technologies are used to successfully fabricate a 4 KG 0.25 µm CMOS gate-array LSI on a BiCMOS test chip of 12 mm square, which operates at 58 ps/G at 2 V. This result demonstrates that SOR lithography will pave the way for the fabrication of sub-0.25-µm BiCMOS ULSIs.

Dislocation-free thin silicon layers are created on the three kinds of substrates such as oxide film, synthetic quartz glass and sapphire. They are bonded with silicon wafers using hydrogen bonding at room temperature but without any adhesive, and their bonding are changed into covalent bonding at elevated temperature. Thick (2 µm) silicon layers are first produced by surface grinding and polishing, and then thinned to 0.1 µm by plasma assisted chemical etching (PACE). A multiple repeated process of thinning the silicon layer and annealing the bonded silicon/quartz and silicon/sapphire interface is applied for tight bonding between a silicon wafer and a quartz wafer, and a silicon wafer and a sapphire wafer which have different thermal expansion coefficients. In case of bonding with sapphire, oxide with 200 in thickness plays an important role in the preventions of void formation and diffusion of interface contaminants into the silicon layer.

This paper proposes a buried-LATID structure featuring a peaked vertical profile around gate edge for the n- drain unlike the reported conventional LATID structure. As compared to the conventional LATID FETs, the deep-submicron buried-LATID FETs achieve improved circuit speed by 7% (50% compared to LDD FETs) due to suppressed gate-to-drain capacitance and improved lifetime by 10 times (300 times compared to LDD FETs). The buried-LATID FETs are very promising for deep-submicron MOSFETs to achieve improved performance and hot-carrier reliability at the same time.

This paper describes a color segmentation method which is essential for automatic diagnosis of stained images. This method is applicable to the variance of input images using a three-layered neural network model. In this network, a back-propagation algorithm was used for learning, and the training data sets of RGB values were selected between the dark and bright images of normal mammary glands. Features of both normal mammary glands and breast cancer tissues stained with hematoxylin-eosin (HE) staining were segmented into three colors. Segmented results indicate that this network model can successfully extract features at various brightness levels and magnifications as long as HE staining is used. Thus, this color segmentation method can accommodate change in brightness levels as well as hue values of input images. Moreover, this method is effective to the variance of scaling and rotation of extracting targets.

A new evaluation technique of hot carrier degradation is proposed and applied to practical evaluation of p-channel polycrystalline silicon thin film transistors (TFT). The proposed technique introduces emission microscopy which is particularly effective for evaluating TFT devices. We have developed an automatic measurement system in which measurement of the electrical characteristics and monitoring the photo emission are done simultaneously. Using this system, we have identified the dominant mechanism of hot carrier degradation in TFTs, and evaluated the effect of plasma hydrogenation on hot carrier degradation.

The power transfer characteristics of a symmetric nonlinear directional coupler (NLDC) are analyzed rigorously using the beam propagation method based on the finite difference scheme. The NLDC consists of two linear waveguides separated by a Kerr-like nonlinear gap layer. The change of nonlinear refractive index along the coupler is precisely evaluated by making use of the second-order iteration procedure with respect to a small propagation length. For the incidence of TE0 mode of the isolated linear waveguide, the highly accurate numerical results are obtained for the behavior of power transfer, and the coupling length and critical power for optical switching. The dependencies of the coupling length and critical power on the width of the gap layer and the input power levels are discussed, compared with those predicted by the coupled-mode approximations.

Junction leakage current of trench isolation devices is strongly influenced by trench configuration. The origin of the leakage current is the mechanical stress that is generated by the differential thermal expansion between the Si substrate and the SiO2 filled isolation trench during the isolation forming process. A two-dimensional mechanical stress simulation was used to analyze trench-isolated devices. The simulated distribution and magnitude of stress were found to agree with Raman spectroscopic measurements of actual devices. The stress in the deeper regions between deep trenches is likely to increase greatly as the size of devices diminishes, so it is important to reduce this stress and thus suppress junction leakage current.