In this paper we propose a new timing optimization technique for multi-level networks by restructuring multiple nodes simultaneously. Multi-output subcircuits on critical paths are extracted and resynthesized so that the delays of the paths are reduced. The complete design space of the subcircuits is captured by Boolean relations, which allow us to perform more powerful resynthesis than previous approaches using don't cares. Experimental results are reported to show the effectiveness of the proposed technique.

This letter extends the overfitting lattice filter for ARMA parameter estimation with additive noise proposed by Sun and Yahagi. A new way of calculating the lattice parameters is proposed, making their computation truly recursive. This simplifies the method in Ref.(1), and makes it suitable to the parameter estimation of high-order systems.

In a coherent optical communication system, a polarization fluctuation of an optical fiber is one of the most important problem. On the other hand, for a realization of optical devices, dielectric waveguides with sinusoidally varying width are investigated. Knowledge of the electromagnetic field distribution in a dielectric waveguide with boundary perturbed time by time becomes a very interesting problem. This paper shows a numerical method to simulate the effect of the external disturbance against the dielectric waveguide from time to time. The author has discussed body fitted grid generation with moving boundary for the Poisson's equation and the Laplace's equation. Here we apply this theory for the dielectric waveguide. The technique employs a kind of an expanded numerical grid generation. As the author added time component to grid generation, the time dependent coordinate system which coincides with a contour of moving boundary could be transformed into fixed rectangular coordinate system. Two cases of the perturbations against the dielectric waveguide are treated. In the first case, we present the electric distribution in the dielectric waveguide perturbed along a propagation path. While in the second case, the electric field in the waveguide perturbed perpendicular to the propagation path. Such phenomena that the phase of the electric field modulated by the external perturbation are clarified by numerical results. This technique makes it possible not only to analyze the effect of the external disturbance in a coherent optical communication system but also to fabricate optical modulators or couplers.

This paper discusses multiple-valued memory circuit using floating gate devices. It is an object of the paper to provide a new and improved analog memory device, which permits the memory of an amount of charges that accurately corresponds to analog information to be stored.

In this paper, four simple nonlinear circuits with time-varying resistors are analyzed. These circuits consist of only four elements; a inductor, a capacitor, a diode and a time-varying resistor and are a kind of parametric excitation circuits whose dissipation factors vary with time. In order to analyze chaotic phenomena observed from these circuits a degeneration technique is used, that is, diodes in the circuits are assumed to operate as ideal switches. Thereby the Poincar maps are derived as one-dimensional maps and chaotic phenomena are well explained. Moreover, validity of the analyzing method is confirmed theoretically and experimentally.

Responses in the Nagumo neural circuit to pulse-train stimulation are studied using the time sequence, phase diagram, Poincare section, return map, firing rate, Lyapunov number and bifurcation diagram. For the mono-stable neuron with an equilibrium point deeper than the maximal point of a tunnel diode curve, main responses are periodic or all-or-none and chaotic responses are rarely observed. For the neuron with an equilibrium point located near the maximal point, the response to one input pulse oscillates after the undershoot and responses to pulse-trains make complex bifurcation structure in the threshold diagram. The ranges of periodic responses are stratified in the diagram. There exist broad regions of chaotic responses and chaos is not a special response of the Nagumo circuit, but it often comes out. The results are different from those obtained from Hodgkin-Huxley equations and the BVP model.

This paper proposes a new admission control strategy for ATM networks, which is based on the simulation approach and regression results. Instead of using many traffic descriptors, in our strategy only numbers of connections of different types are needed in performing admission control. The strategy is evaluated from different points of view, real-time, safety, policing and its efficiency which is referred as allowed utilized bandwidth. Since the admission criteria is developed in a form of regression model, the computation of performance for accepting a new connection is quick and easy. Using the confidence region in statistics to represent the admission criteria, a conservative estimation of performance can be achieved. Besides, this strategy is quite independent, thus can be compatible with most policing functions. Finally, its bandwidth utilization is found to be above 0.54. However, the success of this strategy still depends on the reality of input traffic model. Whenever the traffic can be clearly described, the proposed strategy can be easily and precisely applied. Therefore, we also build a traffic model for different type of traffic including constant-bit-rate (CBR), variable-bit-rate (VBR) and bursty traffic. The application of the proposed strategy to different multiplexing schemes, like priority queues and polling system, etc., should be further studied. Considering different level of performance requirement for different type of traffic, which should aid the bandwidth utilization of this strategy, is also an interesting research issue.

Asynchronous Transfer Mode (ATM) is an information transport technique that well supports Broadband ISDN (B-ISDN). One unsolved problem to the perfection of ATM networks is to provide a testing environment that conforms to some standardized network management scheme. From this point of view, remotely controlled virtual path testing is considered in this paper. Remotely controlled virtual path testing should be executed through the standardized Telecommunications Management Network (TMN) model, which employs the OSI systems management concept as the basis of information exchange. Thus, this paper addresses the two issues that arise when OSI systems management standards are applied to virtual path testing. One issue is to define relevant information models. The other issue is to provide test resources with a concurrency control mechanism that guarantees a consistent test environment without causing deadlocks. To resolve these issues, technical requirements are clarified for the remote control of test resources. Next, alternatives to the concurrency control mechanism are shown and compared through computer simulations. A method of defining information models is then proposed. The proposed method ensures the easy storage and retrieval of intermediate test results as well as permitting the effective provision of concurrency control for test resources. An application scenario is also derived. The scenario shows that tests can be executed by using standardized communication services. These results confirm that virtual path testing can be successfully achieved in conformance with the OSI systems management standards.

In conventional trellis coded modulation (TCM), a bit rate of m/m+1 convolutional encoder is employed for n information bits (mn), where 2n+1 signal points are required. In this paper, we propose a novel TCM system using totally overlapped signal sets (TO-TCM), i.e., each signal point is used twice. Thus, TO-TCM can realize only half signal points (2n) comparing with those of a conventional TCM system (2n+1), and it is possible to implement a coded modulation system without doubling the signal points by an insertion of redundant bits. The cases of the proposed schemes which have a process to extend the minimum free distances between the signal points can achieve a considerable coding gain in comparison to the traditional uncoded systems with 2n signal points. Moreover, as the proposed scheme needs only half signal points (2n) of those of conventional TCM, the average power is lower and it is less sensitive to the carrier phase offset.

This letter describes a new input and cross-point buffering matrix switching architecture for high-speed ATM switching systems. The proposed switch has input queuing buffers at each input port, and small size buffers for output port arbitration at each cross-point. These two types of buffers share loads using a simple and high-speed retry algorithm. Hardware size is only half that of conventional cross-point buffering switches. In addition, the switch achieves high-throughput at a condition that the switching speed matches the input and output port speed. This switch is expected to enable the development of high-speed ATM switching systems with each port supporting speeds in excess of 1Gbit/s.

This paper discusses a formulation of a basic theory of the information systems, where information is not only transmitted, but is also processed and memorized during the transmission. A deterministic procedure applied by an information system is defined as a logical work, and two measurements with information X, information quantity I(X) and information vitality T(X), are introduced. A system with the ability of transmitting, processing and memorizing information is called an information engine. A system of interconnected information engines is called an information network. The power of an information engine is defined as the maximum capacity of the logical works performed by the engine, and important properties of total power of information network are derived. Response time characteristics and cost minimizing problems of an information network are also discussed.

The evolution of Multiple-Valued Logic (MVL) circuits has been inexorably tied to the rapid technological changes induced by evolving needs and emerging developments in computing methodologies. Unfortunately for MVL, the numbers of designers of technologies and circuits whose lives are dedicated to the improvement of binary techniques, are large and overwhelming. Correspondingly, technological developments in MVL typically await the appearance of a problem or technique in the larger binary world to motivate and/or make possible some new advance. Such opportunities are inevitably quite transient since each such problem is simultaneously attacked by many others of a more conventional bent, and, as well, each technological change begets yet another, quickly. It is in the sensing of this reality that the present paper is written. Correspondingly, its thrust is two-fold: One target is the possibility of encouraging a leap ahead through modest technological projection. The other is the possibility of identifying application areas that already exist in this unbalanced competition, but which are specially suited to multiple-valued solutions. For example, it has been clear for decades that one such area is that of arithmetic. Correspondingly, we in MVL must strive quickly to concentrate our efforts on applications that exploit such demonstrable strengths. Some such applications are includes here; others are visible historically, many probably remain to be found: Search on!

A technique is presented for constructing (d,k) block codes capable of detecting single bit errors and single peak-shift errors in consecutive two runs. This constrains the runlengths in the code sequences to odd numbers. The capacities and the cardinalities for finite code length of these codes are described. A technique is also proposed for constructing (d,k) block codes capable of correcting single peak-shift errors.

A fail-safe logic operation refers to such a processing operation that the output assumes the logical value zero when the operation circuit fails. The fail-safe multiple-valued logic operation is proposed as one method of logic operation. Section 2 defines the fail-asfe multiple-valued logic operation and presents an example of method for accomplishing the fail-safe multiple-valued logic operation. Section 3 describes the method of designing a fail-safe threshold operation device (window comparator) as basic device in the fail-safe multiple-valued logic operation in consideration of LSI implementation and shows an example of prototype fail-safe window comparator. This operation device has higher and lower thresholds. It oscillates and produces an operational output signal only when the input signal level falls between the higher and lower thresholds. Unless the fail-safe window comparator is supplied with input signals of higher voltage than the power supply voltage, it dose not form a feedbadk loop as required for it to oscillate. This characteristic prevents the device from erroneously producing an output signal when any failure occurs in the amplifiers comprising the oscillation circuit. The window comparator can be built as a fail-safe threshold operation device. The fail-safe characteristic is utilized in its LSI implementation. Section 4 verifies the fail-safe property of the prortotype fail-safe window comparator. It is shown that even when the LSI develops failures not evident from outsid (latent failures), it does not lose the operational function and maintains the fail-safe characteristic.

Broadband multimedia information environments are part of the next big advance in communications and computer technology. The use of multimedia infrastructures in offices is becoming very important. This paper deals with a service concept and human interfaces based on a paper metaphor. The proposed service offers the advantages of paper and eliminates the disadvantages. The power of multimedia's expressiveness, user interaction, and hypermedia technology are key points of our solution. We propose a system configuration for implementing the service/human interface.

A new method is proposed for automatically evaluating the English pronunciation quality of non-native speakers. It is assumed that pronunciation can be rated using three criteria: the static characteristics of phonetic spectra, the dynamic structure of spectrum sequences, and the prosodic characteristics of utterances. The evaluation uses speech recognition techniques to compare the English words pronounced by a non-native speaker with those pronounced by a native speaker. Three evaluation measures are proposed to rate pronunciation quality. (1) The standard deviation of the mapping vectors, which map the codebook vectors of the non-native speaker onto the vector space of the native speaker, is used to evaluate the static phonetic spectra characteristics. (2) The spectral distance between words pronounced by the non-native speaker and those pronounced by the native speaker obtained by the DTW method is used to evaluate the dynamic characteristics of spectral sequences. (3) The differences in fundamental frequency and speech power between the pronunciation of the native and non-native speaker are used as the criteria for evaluating prosodic characteristics. Evaluation experiments are carried out using 441 words spoken by 10 Japanese speakers and 10 native speakers. One half of the 441 words was used to evaluate static phonetic spectra characteristics, and the other half was used to evaluate the dynamic characteristics of spectral sequences, as well as the prosodic characteristics. Based on the experimental results, the correlation between the evaluation scores and the scores determined by human judgement is found to be 0.90.

A new class of the universal representation for the positive integers is proposed. The positive integers are divided into infinite groups, and each positive integer n is represented by a pair of integers (p,q), which means that n is the q-th number in the p-th group. It is shown that the new class includes the message length strategy as a special case, and the asymptotically optimal representation can easily be realized. Furthermore, a new asymptotically and practically efficient representation scheme is proposed, which preserves the numerical, lexicographical, and length orders.

We have developed a new functional MOS transistor called Neuron MOSFET (abbreviated as neuMOS or νMOS) which simulates the function of biological neurons. The new transistor is capable of executing a weighted sum calculation of multiple input signals and threshold operation based on the result of weighted summation, all in the voltage mode at a single transistor level. By utilizing its neuron-like very powerful functional capability, various circuits essential for multiple-valued logic operation have been designed using quite simple circuit configurations. The circuit designs for data conversion between the multivalued and binary logic systems and for generating universal literal functions are described and their experimental verifications are presented. One of the most important features of νMOS multivalued lagic circuit is that the circuit operates basically in the voltage mode, thus greatly reducing the power dissipation as compared to the conventional current mode circuitry. This is indeed most essential in implementing multivalued logic systems in ultra large scale integration. Another important feature of νMOS design is in its flexibility of implementing logic functions. The functional form of a universal literal function, for instance, can be arbitrarily altered by external signals without any modifications in its hardware configuration. A circuit representing multiple-valued multithreshold functions is also proposed.

Two computational-geometric approaches to linear programming are surveyed. One is based on the prune-and-search paradigm and the other utilizes randomization. These two techniques are quite useful to solve geometric problems efficiently, and have many other applications, some of which are also mentioned.

We consider an asymptotically sparsely encoded associative memory. Patterns are encoded by n-dimensional vectors of 1 and 1 generated randomly by a sequence of biased Bernoulli trials and stored in the network according to Hebbian rule. Using a heuristic argument we derive the following capacities:c(n)ne/4k log n'C(n)ne/4k(1e)log n'where, 0e1 controls the degree of sparsity of the encoding scheme and k is a constant. Here c(n) is the capacity of the network such that any stored pattern is a fixed point with high probability, whereas C(n) is the capacity of the network such that all stored patterns are fixed points with high probability. The main contribution of this technical paper is a theoretical verification of the above results using the Poisson limit theorems of exchangeable events.