In this paper we present a method to generate test sequences for stuck-at faults in sequential circuits which have distinguishing sequences. Since the circuit may have no distinguishing sequence, we use two design techniques for circuits which have distinguishing sequences. One is at state transition level and the other is at gate level. In our proposed method complete test sequence can be generated. The sequence consists of test vectors for the combinational part of the circuit, distinguishing sequences and transition sequences. The test vectors, which are generated by a combinational test generator, cause faulty staes or faulty output responses for a fault, and disinguishing sequences identify the differences between faulty states and fault free states. Transition sequences are necessary to make the state in the combinational vectors. And the distinguishing sequence and the transition sequence are used in the initializing sequence. Some techniques for shortening the test sequence is also proposed. The basic ideas of the techniques are to use a short initializing sequence and to find the order in concatenating sequences. But fault simulation is conducted so as not to miss any faults. The initializing sequence is obtained by using a distinguishing sequence. The efficiency of our method is shown in the experimental results for benchmark circuits.

A modern architect can not design high performance computer architecture without thinking all factors of performance from hardware level (logic/layout design) to system level (application programs, operating systems, and compilers). For computer architecture design, there are few practical CAD tools, which support design activities of the architect. In this paper, we propose a CAD tool, called COACH, for computer architecture design. COACH supports architecture design from hardware level to system level. To make a high-performance general purpose computer system, the architect evaluates system performance as well as hardware level performance. To evaluate hardware level performance accurately, logic/layout synthesis tools and simulator are used for evaluation. Logic/layout synthesis tools translate the architecture design into logic circuits and layout pattern and simulator is used to get accurate information on hardware level performance which consists of clock frequency, the number of transistors, power consumption, and so on. To evaluate system level performance, a compiler generator is introducd. The compiler generator generates a compiler of a programming language from the desripition of architecture design. The designed architecture is simulated in the behavior level with programs compiled by the compiler, and the architect can get information on system level performance which consists of program execution steps, etc. From both hardware level performance and system level performance, the architect can evaluate and revise his/her architecture, considering the architecture from hardware level to system level. In this paper, we propose a new design methodology which uses () logic/layout synthesis tools and simulators as tools for architecture design and () a compiler generator for system level evaluation. COACH, a CAD system based on the methodology, is discussed and a prototype of COACH is implemented. Using the design methodology, two processors are designed. The result of the designs shows that the proposed design methodology are effective in architecture design.

This paper presents a Reconfigurable Machine (RM). capable of efficiently implementing a wide range of computationlly complex algorithms. Its highly flexble architecture combining FPGA's with RAM's supports a wide range of applications. Since its "gate-level programmability" allows us to implement various kinds of parallel processing techniques, RM provides a perfomance comparable to exising "special-purpose" engines. The in-circuit reconfiguration capability of FPGA's is used to reload several kinds of configuration data during power on. Thus, RM behaves itself like a general-purpose computer applicable to various kinds of applications by loading programs. A Reconfigurable Machine-(RM-) has been built as the first prototype incorporating five FPGA's and four SRAM memory banks. RM- has been applied to a multiple-delay Logic Simulator (LSIM). Employing pipeline architecture, LSIM has achieved a perfomance of l million gate events per second at 4MHz. The concept of RM is the best solution to the trade-offs between general-purpose machines and special-purpose ones. RM will be a hardware platform accelerating a wide range of applications, also offering an interesting problem in high-level synthesis.

We present an extension of the previously proposed 3-layer feedforward network called a cascaded network. Cascaded networks are trained to realize category classification employing binary input vectors and locally represented binary target output vectors. To realize a nonlinearly separable task the extended cascaded network presented here is consreucted by introducing high order cross producted inputs at the input layer. In the construction of the cascaded network, two 2-layer networks are first trained independently by delta rule and then cascaded. After cascading, the intermediate layer can be understood as a hidden layer which is trained to attain preassigned saturated outputs in response to the training set. In a cascaded network trained to categorize binary image patterns, saturation of hidden outputs reduces the effect of corrupted disturbances presented in the input. We demonstrated that the extended cascaded network was able to realize a nonlinearly separable task and yielded better generalization ability than the Backpropagation network.

The character binarization method MTC is developed for enhancing the recognition of characters in general outdoor images. Such recognition is traditionally difficult because of the influence of illumination changes, especially strong shadow, and also changes in character, such as apparent character sizes. One way to overcome such difficulties is to restrict objects to be processed by using strong hypotheses, such as type of object, object orientation and distance. Several systems for automatic license plate reading are being developed using such strong hypotheses. However. their strong assumptions limit their applications and complicate the extension of the systems. The MTC method assumes the most reasonable hypotheses possible for characters: they occupy plane areas, consist of narrow lines, and external shadow is considerably larger than character lines. The first step is to eliminate the effect of local brightness changes by enhancing feature including characters. This is achieved by applying mathematical morphology by using a logarithmic function. The enhanced gray-scale image is then binarized. Accurate binarization is achieved because local thresholds are determined from the edges detected in the image. The MTC method yields stable binary results under illumination changes, and, consequently, ensures high character reading rates. This is confirmed with a large number of images collected under a wide variety of weather conditions. It is also shown experimentally that MTC permits stable recognition rate even if the characters vary in size.

We propose a third-order low-pass notch filter realized by a single operational amplifier and a minimum number of equal-valued capacitors. As a design example we realize a Chebyshev filter with a ripple of 0.5 dB and it is shown that the experiment result is very good.

A fully focused Synthetic Aperture Radar (SAR) image can be obtained only if the raw data processing procedure takes into account the space-variance of the SAR system transfer function. This paper presents a nonconventional Fast Fourier Transform (FFT) algorithm which allows an efficient compensation of the space-variant effect. It is specially designed for the SAR data of the Japanese Earth Resources Satellite (JERS-1) but can be extended to different cases.

A multi-beam airborne pulsed-Doppler radar (MBR) system is presented and its clutter rejection performance compared with conventional phased array radar (PAR)'s by PRF tuning is discussed. The pulsed-Doppler radar equations taking account of the multi-beam operation are introduced and some kinds of computer simulations for seeking the conditions to get maximum signal to clutter ratio are carried out. As a results of this, it is cleared that same order of signal to clutter ratio improvement gotten in high PRF operation by conventional PAR can be realized at lower PRF operation by MBR on clutter free area, and higher clutter rejection effect, which is proportional to beam numbers, is obtained under affection of both of mainlobe and sidelobe clutters with order of beam numbers. This also means observable numbers of range bin are increased in MBR operation.

In the future, it will be necessary that robot technology or environmental technology has an auditory function of recognizing sound expect for speech. In this letter, we propose a recognition system for the species of birds receiving birdcalls, based on network technology. We show the first step of a recognition system for the species of birds, as an application of a recognition system for environmental sound.

In the ISAR (Inverse Synthetic Aperture Radar), when a target is to be recognized by use of the radar image produced from the radar echoes, it is important first to estimate the scale of the target. To estimate the scale, the rotating motion of the target must be estimated. This paper describes a method for estimating the scale of the target from the information on the radar image by converting the target figure into a simple model and estimating the rotating motion of the target.

Since the time required for testing logic circuits is proportional to the number of test vectors, the size of test sets as well as test generation time is one of the most important factors to be considered in test generation. The size of test sets becomes an essential issue, especially for scan designed circuits, because of the need to shift a test vector serially into the scan path. In this paper, we propose new methods of generating compact test sets to detect al the irredundant single stuck-at faults in combinational circuits. The proposed algorithms calculate a test function for each fault which corresponds to the set of all test vectors for the fault and generate a compact test set by analyzing the test functions. The analysis is based on finding a test vector which detects the largest number of remaining faults. Since our methods select a test vector among all the test vectors, represented by a test function, for a target fault, smaller test sets can be generated, in general, than that by conventional test set compaction methods. The experimental results show that the size of test sets generated by our method is about one-third as large as that without compaction.

Gamma(γ)-ray irradiation effects have been investigated on three types of low-noise HEMTs, AlGaAs/GaAs conventional HEMT (conv. HEMT), AlGaAs/InGaAs pseudomorphic HEMT (P-HEMT) and InAlAs/InGaAs/InP HEMT (InP-based HEMT). The dose of irradiated γ-rays ranges from 1105 to 1108 rad. DC and RF characteristics of each type of HEMT are measured before and after irradiation and the parameter changes are investigated. For conv. HEMT and P-HEMT, no degradation of DC parameter is observed up to 108 rad, while noise figure (NF) at 12 GHz remains constant up to 107 rad and degrades by 0.1 dB at 108 rad. The InP-based HEMT shows IDSS and gm increase by about 10% at a dose of 108 rad and its NF at 18 GHz lowers gradually with the radiation dose. It has been found that the radiation hardness is greater than 107 rad for all types of HEMTs and over a hundred years of life can be expected against γ-ray irradiation in the space environment.

A coherent communication system using squeezed light is one of candidates for a realization of super-reliable systems. In order to design such a system, it is essential to understand and to analyze modulators mathematically. However, quantum noise of squeezed light has a colored spectrum which changes with respect to phase of a local laser. Therefore the optimization of the relationship between signal and quantum noise spectrums is required at a modulator to obtain the ultimate performance of the communication system. In this paper, some ideas of modulators for squeezed light are proposed and their spectrum transformations are given. After the brief summary of squeezed quantum noise, a new concept which originates from the restriction of the local laser phase is applied to it. This concept makes a problem originated from a colored quantum noise spectrum more serious. It results in the optimization problem for the relationship between the quantum noise spectrum and signal power spectrum. The solution of this problem is also given under the restriction of local laser phase. As a result, a general design theory for coherent communication system using the squeezed light is given.

This paper describes IC-oriented high-performance AlGaAs/GaAs heterojunction bipolar transistors that were fabricated to demonstrate their great potential in applications to high-speed integrated circuits. A collector structure of ballistic collection transistors with a launcher (LBCTs) shortens the intrinsic delay time of the transistors. A novel and simple self-aligned fabrication process, which features an base-metal-overlaid structure (BMO), reduces emitter- and base-resistances and collector capacitance. The combination of the thin-collector LBCT layer structure and the BMO self-alignment technology raises the average value of cutoff frequency, fT, to 160 GHz with a standard deviation as small as 4.3 GHz. By modifying collector thickness and using Pt/Ti/Pt/Au as the base ohmic contact metal in BMO-LBCTs, the maximum oscillation frequency, fmax, reaches 148 GHz with a 114 GHz fT. A 2:1 multiplexer with retiming D-type flip-flops (DFFs) at input/output stages fabricated on a wafer with the thin-collector LBCT structure operates at 19 Gbit/s. A monolithic preamplifier fabricated on the same wafer has a transimpedance of 52 dBΩ with a 3-dB-down bandwidth of 18.5 GHz and a gain S21 OF 21 dB with a 3-dB-down bandwidth of 19 GHz. Finally, a 40 Gbit/s selector IC and a 50 GHz dynamic frequency divider that were successfully fabricated using the 148-GHz fmax technologies are described.

This paper reports performance improvement in an optical fiber feeder for microcellular mobile radio systems. A low noise optical receiver using a transformer resonant circuit is described. With this receiver, CNR degradation due to receiver noise is suppressed to less than 0.9dB. Furthermore, two novel techniques, the use of a multiple-LD transmitter and automatic LD input level control, are proposed. The multiple-LD transmitter increases transmitter output power and reduces the transmitter noise. With a dual-LD transmitter, it is possible to increase the optical loss margin by 3.1dB, which corresponds to transmission length expansion of 6.2km, or to improve the received CNR by 2.8dB, which enables communication range expansion. Automatic LD input level control, which optimizes LD input level according to the received radio power, can expand the actual dynamic range of the up link.

Redundancy is introduced by sampling a bandlimited signal at a higher rate than the Nyquist rate. In the cases of erasures due to fading or jamming, the samples are discarded. Therefore, what we get at the output of the receiver is a set if nonuniform samples obtained from a uniform sampling process with missing samples. As long as the rate of nonuniform samples is higher than the Nyquist rate, the original signal can be recovered with no errors. The sampling theorem can be shown to be equivalent to the fundamental theorem of information theory. This oversampling technique is also equivalent to a convolutional code of infinite constraint length is the Field of real numbers. A DSP implementation of this technique is through the use of a Discrete Fourier Transform (DFT), which happens to be equivalent to block codes in the field of real numbers. An iterative decoder has been proposed for erasure and impulsive noise, which also works with moderate amount of additive random noise. The iterative method is very simple and efficient consisting of modules of Fast Fourier Transforms (FFT) and Inverse FFT's. We also suggest a non-linear iterative method which converges faster than the successive approximation. This iterative decoder can be implemented in a feedback configuration. Besides FFT, other discrete transforms such as Discrete Cosine Transform, Discrete Sine Transform, Discrete Hartley Transform, and Discrete Wavelet Transform are used. The results are comparable to FFT with the advantage of working in the field of real numbers.

This paper presents a potential FM double modulation technique for subcarrier optical transmission in order to improve the input dynamic range. The proposed theory of FM double modulation is presented. The BER performance and input dynamic range are shown theoretically and experimentally compared with conventional direct intensity modulation. It was found that the dynamic range could be experimentally improved by 20dB compared with the conventional method by using FM double modulation. The proposed technique achieved an input dynamic range of 60 dB even when using a commercial Fabri-Perot LD.

Atmospheric optical communication (AOC) system using subcarrier PSK modulation is proposed and its superiority to OOK modulation in the presence of scintillation is discussed theoretically. An experimental AOC setup with a subcarrier modulated by 155.52(Mb/s) DPSK at light wave-length λ=0.83(µm) over an 1.8(km) outdoor path is employed to show the performance. Theoretical and experimental results are compared under scintillation in clear weather and a good agreement is observed. Finally, AOC systems using subcarrier M-ary PSK and multiple subcarriers are proposed and discussed.

This paper describes the performance of AlGaAs/GaAs HBT's developed for power applications. Their applicability to power amplifiers used in digital mobile radio communications is examined through measurement and numerical simulation, considering both power capability and linearity. Power HBT's with carbon-doped base layers showed DC current gains over 90. A linear gain of 19.2 dB, a maximum output RF power of 32.5 dBm, and a power added efficiency of 56 percent were obtained at 950 MHz. Numerical simulations showed that the power efficiency of HBT amplifiers could be improved by using harmonic trap circuits. Intermodulation measurements showed that third-order distortions were at most 21 dBc level at the 1-dB gain compression point. RF spectrum simulations using π/4 shift QPSK modulation showed that side-band spectrum generation was less than 45 dBc level at points 50 kHz off of the carrier frequency. These properties indicate that the power handling capabilities and linearity of HBT amplifiers offer promising potentials for digital mobile radio communications.

In this study, an expression of the regression relationship with less information loss is concretely derived in the form suitable to the existence of amplitude constraint of the observed data and the prediction of response probability distribution. The effectiveness of the proposed method is confirmed experimentally by applying it to the actual acoustic data.