The search functionality is under construction.
The search functionality is under construction.

Keyword Search Result

[Keyword] ATI(18690hit)

18181-18200hit(18690hit)

  • A Dielectric Rod Waveguide Applicator for Microwave Hyperthermia

    Ryoji TANAKA  Yoshio NIKAWA  Shinsaku MORI  

     
    PAPER-Electronic and Radio Applications

      Vol:
    E76-B No:6
      Page(s):
    703-708

    A dielectric rod waveguide applicator for microwave heating such as microwave hyperthermia is described. The applicator consists of the acrylic cylinder filled with deionized water. By circulating the deionized water, the dielectric rod waveguide applicator acts as a surface cooling device, so that it doesn't need any bolus. This surface cooling device enables the dielectric rod waveguide applicator to control the site of effective heating region along the depth axis. Useful pattern of the circular or spheroidal shape and axially symmetric effective heating region were obtained. Furthermore metal strips provided on the aperture of applicator control the shape of the heating pattern.

  • Analysis of Transient Spectral Spread of Directly Modulated DFB LD's

    Takeshi KAWAI  Atsutaka KURIHARA  Masakazu MORI  Toshio GOTO  Akira MIYAUCHI  Takakiyo NAKAGAMI  

     
    PAPER-Optical Communication

      Vol:
    E76-B No:6
      Page(s):
    677-683

    The transient spectral spread of directly modulated DFB LD's, which appears in the time-resolved chirping measurement, is studied experimentally and numerically. Such a phenomenon has been already reported as a side mode oscillation called "subpeak", but there has been little argument as to the physical origin. We make it clear that the subpeak is a spurious mode due to the influence of the photodetector bandwidth. The minimum photodetector bandwidth which is necessary in the time-resolved chirping measurement is examined. Furthermore the distortion of the long-distance transmitted waveform is also explained by one mode oscillation.

  • Critical Slice-Based Fault Localization for Any Type of Error

    Takao SHIMOMURA  

     
    PAPER-Software Systems

      Vol:
    E76-D No:6
      Page(s):
    656-667

    Existing algorithmic debugging methods which can locate faults under the guidance of a system have a number of shortcomings. For example, some cannot be applied to imperative languages with side effects; some can locate a faulty function but cannot locate a faulty statement; and some cannot detect faults related to missing statements. This paper presents an algorithmic critical slice-based fault-locating method for imperative languages. Program faults are first classified into two categories: wrong-value faults and missing-assignment faults. The critical slice with respect to a variable-value error is a set of statements such that (1) a wrong-value fault contained in any instruction in the critical slice may have caused that variable-value error, and (2) a wrong-value fault contained in any instruction outside the critical slice could never have caused that variable-value error. The paper also classifies errors found during program testing into three categories: wrong-output errors, missing-output errors, and infinite-loop errors with no output. It finally shows that it is possible to algorithmically locate any fault, including missing statements, for each type of error.

  • Antenna Gain Measurements in the Presence of Unwanted Multipath Signals Using a Superresolution Technique

    Hiroyoshi YAMADA  Yasutaka OGAWA  Kiyohiko ITOH  

     
    PAPER-Antennas and Propagation

      Vol:
    E76-B No:6
      Page(s):
    694-702

    A superresolution technique is considered for use in antenna gain measurements. A modification of the MUSIC algorithm is employed to resolve incident signals separately in the time domain. The modification involves preprocessing the received data using a spatial scheme prior to applying the MUSIC algorithm. Interference rejection in the antenna measurements using the fast Fourier transform (FFT) based techniques have been realized by a recently developed vector network analyzer, and its availability has been reported in the literature. However, response resolution in the time domain of these conventional techniques is limited by the antenna bandwidth. The MUSIC algorithm has the advantage of being able to eliminate unwanted responses when performing antenna measurements in situations where the antenna band-width is too narrow to support FFT based techniques. In this paper, experimental results of antenna gain measurements in a multipath environment show the accuracy and resolving power of this technique.

  • Computation of Constrained Channel Capacity by Newton's Method

    Kiyotaka YAMAMURA  Shin'ichi OISHI  Kazuo HORIUCHI  

     
    LETTER-Numerical Analysis and Self-Validation

      Vol:
    E76-A No:6
      Page(s):
    1043-1048

    Algorithms for computing channel capacity have been proposed by many researchers. Recently, one of the authors proposed an efficient algorithm using Newton's method. Since this algorithm has local quadratic convergence, it is advantageous when we want to obtain a numerical solution with high accuracy. In this letter, it is shown that this algorithm can be extended to the algorithm for computing the constrained capacity, i.e., the capacity of discrete memoryless channels with linear constraints. The global convergence of the extended algorithm is proved, and its effectiveness is verified by numerical examples.

  • 3-D Object Recognition System Based on 2-D Chain Code Matching

    Takahiro HANYU  Sungkun CHOI  Michitaka KANEYAMA  Tatsuo HIGUCHI  

     
    PAPER-Methods and Circuits for Signal Processing

      Vol:
    E76-A No:6
      Page(s):
    917-923

    This paper presents a new high-speed three-dimensional (3-D) object recognition system based on two-dimensional (2-D) chain code matching. An observed 3-D object is precisely represented by a 2-D chain code sequence from the discrete surface points of the 3-D object, so that any complex objects can be recognized precisely. Moreover, the normalization procedures such as translation, rotation of 3-D objects except scale changes can be performed systematically and regularly regardless of the complexity of the shape of 3-D objects, because almost all the normalization procedures of 3-D objects are included in the 2-D chain code matching procedure. As a result, the additional normalization procedure become only the processing time for scale changes which can be performed easily by normalizing the length of the chain code sequence. In addition, the fast fourier transformation (FFT) is applicable to 2-D chain code matching which calculates cross correlation between an input object and a reference model, so that very fast recognition is performed. In fact, it is demonstrated that the total recognition time of a 3-D ofject is estimated at 5.35 (sec) using the 28.5-MIPS SPARC workstation.

  • Fuzzy Petri Net Representation and Reasoning Methods for Rule-Based Decision Making Systems

    Myung-Geun CHUN  Zeungnam BIEN  

     
    PAPER-Concurrent Systems, Discrete Event Systems and Petri Nets

      Vol:
    E76-A No:6
      Page(s):
    974-983

    In this paper, we propose a fuzzy Petri net model for a rule-based decision making system which contains uncertain conditions and vague rules. Using the transformation method introduced in the paper, one can obtain the fuzzy Petri net of the rule-based system. Since the fuzzy Petri net can be represented by some matrices, the algebraic form of a state equation of the fuzzy Petri net is systematically derived. Both forward and backward reasoning are performed by using the state equations. Since the proposed reasoning methods require only simple arithmetic operations under a parallel rule firing scheme, it is possible to perform real-time decision making with applications to control systems and diagnostic systems. The methodology presented is also applicable to classical (nonfuzzy) knowledge base systems if the nonfuzzy system is considered as a special case of a fuzzy system with truth values being equal to the extreme values only. Finally, an illustrative example of a rule-based decision making system is given for automobile engine diagnosis.

  • On Malign Input Distributions for Algorithms

    Kojiro KABAYASHI  

     
    PAPER-Algorithm and Computational Complexity

      Vol:
    E76-D No:6
      Page(s):
    634-640

    By a measure we mean a function µ from {0, 1}* (the set of all binary sequences) to real numbers such that µ(x)0 and µ({0, 1}*). A malign measure is a measure such that if an input x in {0, 1}n (the set of all binary sequences of length n) is selected with the probability µ(x)/µ ({0, 1}n) then the worst-case computation time tWOA (n) and the average-case computation time tav,µA(n) of an algorithm A for inputs of length n are functions of n of the same order for any algorithm A. Li and Vitányi found that measures that are known as a priori measures are malign. We prove that a priori" -ness and malignness are different in one strong sense.

  • Some Hierarchy Results on Multihead Automata over a One-Letter Alphabet

    Yue WANG  Katsushi INOUE  Itsuo TAKANAMI  

     
    PAPER-Automaton, Language and Theory of Computing

      Vol:
    E76-D No:6
      Page(s):
    625-633

    The hierarchies of multihead finite automata over a one-letter alphabet are investigated. Let SeH(k) [NSeH(k) ] denote the class of languages over a one-letter alphabet accepted by deterministic [nondeterministic] sensing two-way k-head finite automata. Let H (k)s[NH(k)s] denote the class of sets of square tapes over a one-letter alphabet accepted by two-dimensional four-way deterministic [nondeterministic] k-head finite automata. Let SeH(k)s[NSeH(k)s] denote the class of sets of square tapes over a one-letter alphabet accepted by two-dimensional four-way sensing deterministic [nondeterministic] k-head finite automata. This paper shows that SeH(k) SeH(k1) and NSeH(k) NSeH(k1) hold for all k3. It is also shown that H(k)s[NH(k)s] H(k1)s[NH (k1)s] and SeH (k)s[NSeH(k)s] SeH(k1)s[NSeH(k1)s] hold for all k1.

  • Focused Ion Beam Trimming Techniques for MMIC Circuit Optimization

    Takahide ISHIKAWA  Makio KOMARU  Kazuhiko ITOH  Katsuya KOSAKI  Yasuo MITSUI  Mutsuyuki OTSUBO  Shigeru MITSUI  

     
    PAPER

      Vol:
    E76-C No:6
      Page(s):
    891-900

    Focused Ion Beam (FIB) trimming techniques for circuit optimization for GaAs MMICs by adjusting the parameters of IC components such as resistors, capacitors, microstrip lines, and FETs have been developed. The adjustment is performed by etching of the components and depositing of metal films for micro-strip lines. This technology turned out to be in need of only half a day to optimize the circuit pattern without any further wafer processes, while a conventional method that is comprised of revising mask pattern and following several cycles of wafer process has needed 0.5-1.0 year requiring huge amount of development cost. This technology has been successfully applied to optimization of an X-band low dissipation current single stage MMIC amplifier, and has shown its great feasibility for shortening the turn around time.

  • A New Auto-Regressive Equation for Generating a Binary Markov Chain

    Junichi NAKAYAMA  

     
    LETTER-Digital Signal Processing

      Vol:
    E76-A No:6
      Page(s):
    1031-1034

    This paper proposes a second order auto-regressive equation with discrete-valued random coefficients. The auto-regressive equation transforms an independent stochastic sequence into a binary sequence, which is a special case of a stationary Markov chain. The power spectrum, correlation function and the transition probability are explicitly obtained in terms of the random coefficients. Some computer results are illustrated in figures.

  • A Recycling Scheme for Layout Patterns Used in an Old Fabrication Technology

    Yuji SHIGEHIRO  Isao SHIRAKAWA  

     
    PAPER-Algorithms for VLSI Design

      Vol:
    E76-A No:6
      Page(s):
    886-893

    When a new fabrication process is set up, especially in layout design for functional cells, of practical importance is how to make the best use of layout resources so far accumulated in old fabrication processes. Usually layout data of each element are expressed mostly in terms of positional coordinate values, and hence it is extremely tedious to modify them at every change of design rules for a new fabrication technology. To cope with this difficulty, the present paper describes an automatic recycling scheme for layout resources accumulated dedicatedly for functional cell generation. The main subject of this scheme is to transform given layout data into a layout description format expressed in layout parameters. Once layout data are parameterized, layout patterns of functional cells can be reconstructed simply by tuning up parameters in accordance with a new set of design rules. A part of implementation results are also shown.

  • Error Probability Analysis in Reduced State Viterbi Decoding

    Carlos VALDEZ  Hiroyuki FUJIWARA  Ikuo OKA  Hirosuke YAMAMOTO  

     
    PAPER-Communication Theory

      Vol:
    E76-B No:6
      Page(s):
    667-676

    The performance evaluation by analysis of systems employing Reduced State Viterbi decoding is addressed. This type of decoding is characterized by an inherent error propagation effect, which yields a difficulty in the error probability analysis, and has been usually neglected in the literature. By modifying the Full State trellis diagram, we derive for Reduced State schemes, new transfer function bounds with the effects of error propagation. Both the Chernoff and the tight upper bound are applied to the transfer function in order to obtain the bit error probability upper bound. Furthermore, and in order to get a tighter bound for Reduced State decoding schemes with parallel transitions, the pairwise probability of the two sequences involved in an error event is upper bounded, and then the branch metric of a sequence taken from that bound is associated with a truncated instead of complete Gaussian noise probability density function. To support the analysis, particular assessment is done for a Trellis Coded Modulation scheme.

  • Analysis of Excess Intensity Noise due to External Optical Feedback in DFB Semiconductor Lasers on the Basis of Mode Competition Theory

    Michihiko SUHARA  Minoru YAMADA  

     
    PAPER-Opto-Electronics

      Vol:
    E76-C No:6
      Page(s):
    1007-1017

    The generation mechanism for excess intensity noise due to optical feedback is analyzed theoretically and experimentally. Modal rate equations under the weakly coupled condition with external feedback are derived to include the mode competition phenomena in DFB and Fabry-Perot lasers. We found that the sensitivity of the external feedback strongly depends on design parameters of structure, such as the coupling constant of the corrugation, the facet reflection and the phase relation between the corrugation and the facet. A DFB laser whose oscillating wavelength is well adjusted to Bragg wavelength through insertion of a phase adjustment region becomes less sensitive to external optical feedback than a Fabry-Perot laser, but other types of DFB lasers revealing a stop band are more sensitive than the Fabry-Perot laser.

  • Cancellation Technique of Parasitics in Active Filter Design

    Takao TSUKUTAKI  Masaru ISHIDA  Yutaka FUKUI  

     
    LETTER-Methods and Circuits for Signal Processing

      Vol:
    E76-A No:6
      Page(s):
    957-960

    This letter presents a technique to cancel the parasitic effects of operational amplifier (op amp) in active filter design. To minimize the effects, an op amp model considering the parasitics (i.e. both parasitic poles and zeros) is utilized. It is shown that undesirable factors in the transfer function due to the parasitics can be canceled well by predistorting the passive element values of the circuit. As an example, an active-R highpass filter is evaluated both theoretically and numerically. In this way, the proposed technique can be effectively incorporated into the design of active filters.

  • Recessed-Gate Doped-Channel Hetero-MISFETs (DMTs) for High-Speed Laser Driver IC Application

    Yasuyuki SUZUKI  Hikaru HIDA  Tetsuyuki SUZAKI  Sadao FUJITA  Akihiko OKAMOTO  

     
    PAPER

      Vol:
    E76-C No:6
      Page(s):
    907-911

    Recessed-gate DMTs (doped-channel hetero-MISFETs) with i-AlGaAs/n-GaAs structure and pseudomorphic i-AlGaAs/n-InGaAs/i-GaAs structure have been developed. Broad plateaus in gm and fT provide evidence that the DMTs make the devices suitable for high-speed large-signal operation. GaAs DMTs with 0.35 µm-length have gate turn on voltage of 0.7 V, maximum transconductance of 320 mS/mm and fT of 41 GHz. Pseudomorphic DMTs have gate turn on voltage of 0.9 V, maximum transconductance of 320 mS/mm, fT of 42 GHz and have the enhanced advantages of high current drivability and large gate swing. Further more, with the use of the recessed-gate DMTs, a high-speed laser driver IC for multi-Gb/s optical communication systems are demonstrated. This laser driver IC operates at 10 Gb/s with rise and fall times as fast as 40 psec, and it can drive up to 60 mA into a 25 Ω load.

  • Unified Scheduling of High Performance Parallel VLSI Processors for Robotics

    Bumchul KIM  Michitaka KAMEYAMA  Tatsuo HIGUCHI  

     
    PAPER-Parallel Processor Scheduling

      Vol:
    E76-A No:6
      Page(s):
    904-910

    The performance of processing elements can be improved by the progress of VLSI circuit technology, while the communication overhead can not be negligible in parallel processing system. This paper presents a unified scheduling that allocates tasks having different task processing times in multiple processing elements. The objective function is formulated to measure communication time between processing elements. By employing constraint conditions, the scheduling efficiently generates an optimal solution using an integer programming so that minimum communication time can be achieved. We also propose a VLSI processor for robotics whose latency is very small. In the VLSI processor, the data transfer between two processing elements can be done very quickly, so that the communication cycle time is greatly reduced.

  • Single Minimum Method for Combinatorial Optimization Problems and Its Application to the TSP Problem

    Dan XU  Itsuo KUMAZAWA  

     
    PAPER-Neural Nets--Theory and Applications--

      Vol:
    E76-A No:5
      Page(s):
    742-748

    The problem of local minima is inevitable when solving combinatorial optimization problems by conventional methods such as the Hopfield network, relying on the minimization of an objective function E(X). Such a problem arises from the search mechanism in which only the local information about the objective function E(X) is used. In this paper we propose a new approach called the Single Minimum Method (SMM) which uses the global information in searching for the solutions to combinatorial optimization problems. In this approach, we add a function -TS(X) to the original objective function E(X) to construct the function F(X)=E(X)-TS(X) which has only one minimum, one which can be easily found by any general gradiet method including the Hopfield network. Based on an analogy between thermodynamic systems and neural networks, it is shown that the global information about the original objective function E(X) is included in the single minimum of the function F(X) and can be used for finding the global minimum of the objective function E(X). In order to show how to apply the Single Minimum Method to a combinatorial optimization problem we give an algorithm for the TSP problem based on our method. The simulation results show that the algorithm can almost always find the shortest or near shortest paths. Finally, a modified SMM, which has some great advantages for hardware implementation, is also given.

  • Global Unfolding of Chua's Circuit

    Leon O. CHUA  

     
    PAPER-Chaos and Related Topics

      Vol:
    E76-A No:5
      Page(s):
    704-734

    By adding a linear resistor in series with the inductor in Chua's circuit, we obtain a circuit whose state equation is topologically conjugate (i.e., equivalent) to a 21-parameter family C of continuous odd-symmetric piecewise-linear equations in R3. In particular, except for a subset of measure zero, every system or vector field belonging to the family C, can be mapped via an explicit non-singular linear transformation into this circuit, which is uniquely determined by 7 parameters. Since no circuit with less than 7 parameters has this property, this augmented circuit is called an unfolding of Chua's circuit--it is analogous to that of "unfolding a vector field" in a small neighborhood of a singular point. Our unfolding, however, is global since it applies to the entire state space R3. The significance of the unfolded Chua's Circuit is that the qualitative dynamics of every autonomous 3rd-order chaotic circuit, system, and differential equation, containing one odd-symmetric 3-segment piecewise-linear function can be mapped into this circuit, thereby making their separate analysis unnecessary. This immense power of unification reduces the investigation of the many heretofore unrelated publications on chaotic circuits and systems to the analysis of only one canonical circuit. This unified approach is illustrated by many examples selected from a zoo of more than 30 strange attractors extracted from the literature. In addition, a gallery of 18 strange attractors in full color is included to demonstrate the immensely rich and complex dynamics of this simplest among all chaotic circuits.

  • Process and Device Technologies of CMOS Devices for Low-Voltage Operation

    Masakazu KAKUMU  

     
    INVITED PAPER

      Vol:
    E76-C No:5
      Page(s):
    672-680

    Process and device technologies of CMOS devices for low-voltage operation are described. First, optimum power-supply voltage for CMOS devices is examined in detail from the viewpoints of circuit performance, device reliability and power dissipation. As a result, it is confirmed that power-supply voltage can be reduced without any speed loss of the CMOS device. Based upon theoretical understanding, the author suggests that lowering threshold voltage and reduction of junction capacitance are indispensable for CMOS devices with low-voltage supply, in order to improve the circuit performance, as expected from MOS device scaling. Process and device technologies such as Silicon On Insulator (SOI) device, low-temperature operation and CMOS Shallow Junction Well FET (CMOS-SJET) structure are reviewed for reduction of the threshold voltage and junction capacitance which lead to high-seed operation of the COMS device at low-voltage.

18181-18200hit(18690hit)