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7801-7820hit(20498hit)

  • Reduction of Area per Good Die for SoC Memory Built-In Self-Test

    Masayuki ARAI  Tatsuro ENDO  Kazuhiko IWASAKI  Michinobu NAKAO  Iwao SUZUKI  

     
    PAPER-Logic Synthesis, Test and Verification

      Vol:
    E93-A No:12
      Page(s):
    2463-2471

    To reduce the manufacturing cost of SoCs with many embedded SRAMs, we propose a scheme to reduce the area per good die for the SoC memory built-in self-test (MBIST). We first propose BIST hardware overhead reduction by application of an encoder-based comparator. For the repair of a faulty SRAM module with 2-D redundancy, we propose spare assignement algorithm. Based on an existing range-cheking-first algorithm (RCFA), we propose assign-all-row-RCFA (A-RCFA) which assign unused spare rows to faulty ones, in order to suppress the degradation of repair rate due to compressed fail location information output from the encoder-based comparator. Then, considering that an SoC has many SRAM modules, we propose a heuristic algorithm based on iterative improvement algorithm (IIA), which determines whether each SRAM should have a spare row or not, in order to minimize area per a good die. Experimental results on practical scale benchmark SoCs with more than 1,000 SRAM modules indicate that encoder-based comparators reduce hardware overhead by about 50% compared to traditional ones, and that combining the IIA-based algorithm for determining redundancy architecture with the encoder-based comparator effectively reduces the area per good die.

  • A Design Methodology for a DPA-Resistant Circuit with RSL Techniques

    Daisuke SUZUKI  Minoru SAEKI  Koichi SHIMIZU  Akashi SATOH  Tsutomu MATSUMOTO  

     
    PAPER-Logic Synthesis, Test and Verification

      Vol:
    E93-A No:12
      Page(s):
    2497-2508

    A design methodology of Random Switching Logic (RSL) using CMOS standard cell libraries is proposed to counter power analysis attacks against cryptographic hardware modules. The original RSL proposed in 2004 requires a unique RSL-gate for random data masking and glitch suppression to prevent secret information leakage through power traces. In contrast, our new methodology enables to use general logic gates supported by standard cell libraries. In order to evaluate its practical performance in hardware size and speed as well as resistance against power analysis attacks, an AES circuit with the RSL technique was implemented as a cryptographic LSI using 130-nm and 90-nm CMOS standard cell library. From the results of attack experiments that used a million traces, we confirmed that the RSL-AES circuit has very high DPA and CPA resistance thanks to the contributions of both the masking function and the glitch suppressing function.

  • Closed Form Solutions of Joint Water-Filling for Coordinated Transmission

    Bing LUO  Qimei CUI  Hui WANG  Xiaofeng TAO  Ping ZHANG  

     
    PAPER

      Vol:
    E93-B No:12
      Page(s):
    3461-3468

    It is known that traditional water-filling provides a closed form solution for capacity maximization in frequency-selective channels or fading channels with adaptive modulation. However, the solution is derived from a maximum mutual information argument with a single total power constraint. Motivated by the new technology of coordinated multiple point transmission (CoMP), this paper considers a novel power allocation scheme for a frequency-selective fading channel with multiple coordinated transmission points (CTP) transmission, in which each CTP has a power constraint and an individual channel state information (CSI). In order to maximize the channel's throughput, closed form solutions are obtained by solving a non-convex constrained optimization problem. The solution turns out to take the form of traditional WF and also combined with some regular cooperative feature. Based on the derived solution, we firstly investigate a joint water-filling (Jo-WF) power allocation scheme and a new iterative Jo-WF algorithm. Numerical results are presented to verify the optimality of the derived scheme and to show throughput gains over traditional non-coordinated water-filling (WF) and equal power allocation (EPA). Considering the flexibility of CTP's category, e.g., base station or relay station, it is known that the derived Jo-WF power allocation scheme can be valid for any coordinated networks such as next-generation cellular networks or ad-hoc networks.

  • Analytical Study on Performance Improvement of Service Availability in Heterogeneous Radio Networks

    Kanshiro KASHIKI  Tadayuki FUKUHARA  Akira YAMAGUCHI  Toshinori SUZUKI  

     
    PAPER

      Vol:
    E93-B No:12
      Page(s):
    3302-3310

    From the viewpoint of service availability, which is an important evaluation factor in communication quality, we analytically study the performance improvement of heterogeneous radio networks that cooperatively select one system from among multiple communication systems. It is supposed herein that the heterogeneous network selects one system with the larger throughput or with the smaller time delay. To this end, we firstly derive analytical methods using the probability density function of the performance characteristics of the communication systems consisting of the heterogeneous radio network. The analytical method described here is comparatively general and enables the handling of cases where complete cooperation can and cannot be achieved in the heterogeneous network. As for the performance characteristics, we conduct an experiment using the wireless LAN to establish the probability distribution models of the throughput and time delay in the communication system. Using the analytical method and the experimental model obtained, we calculate the performance improvement by cooperative operation in the heterogeneous network. The equational expression to obtain the theoretical performance improvement limit is also investigated through the analytical equations.

  • New Differential Cryptanalytic Results for Reduced-Round CAST-128

    Meiqin WANG  Xiaoyun WANG  Kam Pui CHOW  Lucas Chi Kwong HUI  

     
    PAPER-Cryptography and Information Security

      Vol:
    E93-A No:12
      Page(s):
    2744-2754

    CAST-128 is a block cipher used in a number of products, notably as the default cipher in some versions of GPG and PGP. It has been approved for Canadian government use by the Communications Security Establishment. Haruki Seki et al. found 2-round differential characteristics and they can attack 5-round CAST-128. In this paper, we studied the properties of round functions F1 and F3 in CAST-128, and identified differential characteristics for F1 round function and F3 round function. So we identified a 6-round differential characteristic with probability 2-53 under 2-23.8 of the total key space. Then based on 6-round differential characteristic, we can attack 8-round CAST-128 with key sizes greater than or equal to 72 bits and 9-round CAST-128 with key sizes greater than or equal to 104 bits. We give the summary of attacks on reduced-round CAST-128 in Table 10.

  • Proportional Fair Resource Allocation in Coordinated MIMO Networks with Interference Suppression

    Lei ZHONG  Yusheng JI  

     
    PAPER

      Vol:
    E93-B No:12
      Page(s):
    3489-3496

    The biggest challenge in multi-cell MIMO multiplexing systems is how to effectively suppress the other-cell interference (OCI) since the OCI severely decrease the system performance. Cooperation among cells is one of the most promising solutions to OCI problems. However, this solution suffers greatly from delay and overhead issues, which make it impractical. A coordinated MIMO system with a simplified cooperation between the base stations is a compromise between the theory and practice. We aim to devise an effective resource allocation algorithm based on a coordinated MIMO system that largely alleviates the OCI. In this paper, we propose a joint resource allocation algorithm incorporating intra-cell beamforming multiplexing and inter-cell interference suppression, which adaptively allocates the transmitting power and schedules users while achieving close to an optimal system throughput under proportional fairness consideration. We formulate this problem as a nonlinear combinational optimization problem, which is hard to solve. Then, we decouple the variables and transform it into a problem with convex sub-problems that can be solve but still need heavy computational complexity. In order to implement the algorithm in real-time scenarios, we reduce the computational complexity by assuming an equal power allocation utility to do user scheduling before the power allocation. Extensive simulation results show that the joint resource allocation algorithm can achieve a higher throughput and better fairness than the traditional method while maintains the proportional fairness. Moreover, the low-complexity algorithm obtains a better fairness and less computational complexity with only a slight loss in throughput.

  • Low-Power High-Speed Data Serializer for Mobile TFT-LCD Driver ICs

    Jae-Hyuck WOO  Jae-Goo LEE  Young-Hyun JUN  Bai-Sun KONG  

     
    LETTER-Circuit Design

      Vol:
    E93-A No:12
      Page(s):
    2621-2622

    A novel data serializer is proposed for use in mobile TFT-LCD driver ICs. The proposed data serializer adopting hierarchical switching and repeater/separator schemes provides 82% power reduction and 27% speed improvement with 27% area saving. Measured overall power consumption of a TFT-LCD driver IC with the proposed data serializer was reduced by as much as 49%.

  • An Enhanced Automatic Gain Control Algorithm for Initial Cell Search in 3GPP LTE TDD System

    Jun-Hee JANG  Keun-Dea KIM  Hyung-Jin CHOI  

     
    PAPER-Wireless Communication Technologies

      Vol:
    E93-B No:12
      Page(s):
    3606-3615

    In this paper, we propose an AGC (Automatic Gain Control) algorithm for initial cell search in 3GPP (3rd Generation Partnership Project) LTE (Long Term Evolution) TDD (Time Division Duplex) system. Since the received signal has a large signal power difference between uplink and downlink subframe in wireless communication systems using a TDD scheme, conventional AGC scheme cannot sufficiently adjust the AGC gain because the AGC gain cannot converge fast enough to properly respond. Therefore, conventional AGC scheme leads to increased AGC gain variation, and the received signal will be attenuated by large AGC gain variation. To overcome this limitation, we propose an AGC scheme based on the average amplitude ratio calculation which can not only effectively increase convergence speed of the AGC gain but also maintain the stability of AGC operation in LTE TDD system. Also, it is important for AGC to converge efficiently for the accurate radio frame timing detection during the subsequent initial cell search procedure. Therefore, we also consider the proposed AGC scheme in combination with PSS (Primary Synchronization Signal) detection interface for the first step of initial cell search process in LTE TDD system to obtain both a stable AGC operation and accurate PSS detection performance. By extensive computer simulation in the presence of frequency offset and various channel environments, we verified that the proposed method can obtain a good behavior in terms of demodulation and PSS detection performance in LTE TDD system.

  • Binary Oriented Vulnerability Analyzer Based on Hidden Markov Model

    Hao BAI  Chang-zhen HU  Gang ZHANG  Xiao-chuan JING  Ning LI  

     
    LETTER-Dependable Computing

      Vol:
    E93-D No:12
      Page(s):
    3410-3413

    The letter proposes a novel binary vulnerability analyzer for executable programs that is based on the Hidden Markov Model. A vulnerability instruction library (VIL) is primarily constructed by collecting binary frames located by double precision analysis. Executable programs are then converted into structurized code sequences with the VIL. The code sequences are essentially context-sensitive, which can be modeled by Hidden Markov Model (HMM). Finally, the HMM based vulnerability analyzer is built to recognize potential vulnerabilities of executable programs. Experimental results show the proposed approach achieves lower false positive/negative rate than latest static analyzers.

  • On-Line Electrocardiogram Lossless Compression Using Antidictionary Codes for a Finite Alphabet

    Takahiro OTA  Hiroyoshi MORITA  

     
    PAPER-Biological Engineering

      Vol:
    E93-D No:12
      Page(s):
    3384-3391

    An antidictionary is particularly useful for data compression, and on-line electrocardiogram (ECG) lossless compression algorithms using antidictionaries have been proposed. They work in real-time with constant memory and give better compression ratios than traditional lossless data compression algorithms, while they only deal with ECG data on a binary alphabet. This paper proposes on-line ECG lossless compression for a given data on a finite alphabet. The proposed algorithm gives not only better compression ratios than those algorithms but also uses less computational space than they do. Moreover, the proposed algorithm work in real-time. Its effectiveness is demonstrated by simulation results.

  • SLA-Based Scheduling of Bag-of-Tasks Applications on Power-Aware Cluster Systems

    Kyong Hoon KIM  Wan Yeon LEE  Jong KIM  Rajkumar BUYYA  

     
    PAPER

      Vol:
    E93-D No:12
      Page(s):
    3194-3201

    Power-aware scheduling problem has been a recent issue in cluster systems not only for operational cost due to electricity cost, but also for system reliability. In this paper, we provide SLA-based scheduling algorithms for bag-of-tasks applications with deadline constraints on power-aware cluster systems. The scheduling objective is to minimize power consumption as long as the system provides the service levels of users. A bag-of-tasks application should finish all the sub-tasks before the deadline as the service level. We provide the power-aware scheduling algorithms for both time-shared and space-shared resource sharing policies. The simulation results show that the proposed algorithms reduce much power consumption compared to static voltage schemes.

  • Subtraction Inversion for Delta Path's Hardware Simplification in MASH Delta-Sigma Modulator

    Pao-Lung CHEN  

     
    LETTER-Circuit Design

      Vol:
    E93-A No:12
      Page(s):
    2616-2620

    The multistage noise-shaping (MASH) delta-sigma modulator (DSM) is the key element in a fractional-N frequency synthesizer. A hardware simplification method with subtraction inversion is proposed for delta-path's design in a MASH delta-sigma modulator. The subtraction inversion method focuses on simplification of adder-subtractor unit in the delta path with inversion of subtraction signal. It achieves with less hardware cost as compared with the conventional approaches. As a result, the hardware organization is regular and easy for expanding into higher order MASH DSM design. Analytical details of the implementation way and hardware cost function with N-th order configuration are presented. Finally, simulations with hardware description language as well as synthesis data verified the proposed design method.

  • Parallelization of Computing-Intensive Tasks of the H.264 High Profile Decoding Algorithm on a Reconfigurable Multimedia System

    Tongsheng GENG  Leibo LIU  Shouyi YIN  Min ZHU  Shaojun WEI  

     
    PAPER

      Vol:
    E93-D No:12
      Page(s):
    3223-3231

    This paper proposes approaches to perform HW/SW (Hardware/Software) partition and parallelization of computing-intensive tasks of the H.264 HiP (High Profile) decoding algorithm on an embedded coarse-grained reconfigurable multimedia system, called REMUS (REconfigurable MUltimedia System). Several techniques, such as MB (Macro-Block) based parallelization, unfixed sub-block operation etc., are utilized to speed up the decoding process, satisfying the requirements of real-time and high quality H.264 applications. Tests show that the execution performance of MC (Motion Compensation), deblocking, and IDCT-IQ (Inverse Discrete Cosine Transform-Inverse Quantization) on REMUS is improved by 60%, 73%, 88.5% in the typical case and 60%, 69%, 88.5% in the worst case, respectively compared with that on XPP PACT (a commercial reconfigurable processor). Compared with ASIC solutions, the performance of MC is improved by 70%, 74% in the typical and in the worst case, respectively, while those of Deblocking remain the same. As for IDCT_IQ, the performance is improved by 17% no matter in the typical or worst case. Relying on the proposed techniques, 1080p@30 fps of H.264 HiP@ Level 4 decoding could be achieved on REMUS when utilizing a 200 MHz working frequency.

  • A 9-bit 100-MS/s 1.46-mW Tri-Level SAR ADC in 65 nm CMOS

    Yanfei CHEN  Sanroku TSUKAMOTO  Tadahiro KURODA  

     
    PAPER-Circuit Design

      Vol:
    E93-A No:12
      Page(s):
    2600-2608

    A 9-bit 100-MS/s successive approximation register (SAR) ADC with low power and small area has been implemented in 65-nm CMOS technology. A tri-level charge redistribution technique is proposed to reduce DAC switching energy and settling time. By connecting bottom plates of differential capacitor arrays for charge sharing, extra reference voltage is avoided. Two reference voltages charging and discharging the capacitors are chosen to be supply voltage and ground in order to save energy and achieve a rail-to-rail input range. Split capacitor arrays with mismatch calibration are implemented for small area and small input capacitance without linearity degradation. The ADC achieves a peak SNDR of 53.1 dB and consumes 1.46 mW from a 1.2-V supply, resulting in a figure of merit (FOM) of 39 fJ/conversion-step. The total active area is 0.012 mm2 and the input capacitance is 180 fF.

  • Deafness Resilient MAC Protocol for Directional Communications

    Jacir Luiz BORDIM  Koji NAKANO  

     
    PAPER

      Vol:
    E93-D No:12
      Page(s):
    3243-3250

    It is known that wireless ad hoc networks employing omnidirectional communications suffer from poor network throughput due to inefficient spatial reuse. Although the use of directional communications is expected to provide significant improvements in this regard, the lack of efficient mechanisms to deal with deafness and hidden terminal problems makes it difficult to fully explore its benefits. The main contribution of this work is to propose a Medium Access Control (MAC) scheme which aims to lessen the effects of deafness and hidden terminal problems in directional communications without precluding spatial reuse. The simulation results have shown that the proposed directional MAC provides significant throughput improvement over both the IEEE802.11DCF MAC protocol and other prominent directional MAC protocols in both linear and grid topologies.

  • Analysis of Primary Signal Detection Period in Cognitive Wireless Communications

    Chang-Woo PYO  Hiroshi HARADA  

     
    LETTER

      Vol:
    E93-B No:12
      Page(s):
    3501-3504

    This paper investigates primary signal detection by using a quiet period (QP) in cognitive wireless communications. In particular, we provide an analytical model for studying the impact of QPs on the system performance. Our analysis shows that two successive QPs have a significant impact on system performance. Moreover, the analytical results obtained reveal an optimum period of two successive QPs that maximize system performance.

  • Component Identification and Evaluation for Legacy Systems--An Empirical Study--

    JianFeng CUI  HeungSeok CHAE  

     
    PAPER-Software Engineering

      Vol:
    E93-D No:12
      Page(s):
    3306-3320

    In the field of software reengineering, many component identification approaches have been proposed for evolving legacy systems into component-based systems. Understanding the behaviors of various component identification approaches is the first important step to meaningfully employ them for legacy systems evolution, therefore we performed an empirical study on component identification technology with considerations of their similarity measures, clustering approaches and stopping criteria. We proposed a set of evaluation criteria and developed the tool CIETool to automate the process of component identification and evaluation. The experimental results revealed that many components of poor quality were produced by the employed component identification approaches; that is, many of the identified components were tightly coupled, weakly cohesive, or had inappropriate numbers of implementation classes and interface operations. Finally, we presented an analysis on the component identification approaches according to the proposed evaluation criteria, which suggested that the weaknesses of these clustering approaches were the major reasons that caused components of poor-quality.

  • Accuracy Enhancement of Grid-Based SSTA by Coefficient Interpolation

    Shinyu NINOMIYA  Masanori HASHIMOTO  

     
    PAPER-Device and Circuit Modeling and Analysis

      Vol:
    E93-A No:12
      Page(s):
    2441-2446

    Statistical timing analysis for manufacturing variability requires modeling of spatially-correlated variation. Common grid-based modeling for spatially-correlated variability involves a trade-off between accuracy and computational cost, especially for PCA (principal component analysis). This paper proposes to spatially interpolate variation coefficients for improving accuracy instead of fining spatial grids. Experimental results show that the spatial interpolation realizes a continuous expression of spatial correlation, and reduces the maximum error of timing estimates that originates from sparse spatial grids For attaining the same accuracy, the proposed interpolation reduced CPU time for PCA by 97.7% in a test case.

  • Optimized Spatial Capacity by Eigenvalue Decomposition of Adjacency Matrix

    Fumie ONO  

     
    LETTER

      Vol:
    E93-B No:12
      Page(s):
    3514-3517

    In this letter, an eigenspace of network topology is introduced to increase a spatial capacity. The network topology is represented as an adjacency matrix. By an eigenvector of adjacency matrix, efficient two way transmission can be realized in wireless distributed networks. It is confirmed by numerical analysis that the scheme with an eigenvector of adjacency matrix supplies higher spatial capacity and reliability than that of conventional scheme.

  • Low-Complexity and Energy-Efficient Algorithms on Image Compression for Wireless Sensor Networks

    Phat NGUYEN HUU  Vinh TRAN-QUANG  Takumi MIYOSHI  

     
    PAPER

      Vol:
    E93-B No:12
      Page(s):
    3438-3447

    This paper proposes two algorithms to balance energy consumption among sensor nodes by distributing the workload of image compression tasks within a cluster on wireless sensor networks. The main point of the proposed algorithms is to adopt the energy threshold, which is used when we implement the exchange and/or assignment of tasks among sensor nodes. The threshold is well adaptive to the residual energy of sensor nodes, input image, compressed output, and network parameters. We apply the lapped transform technique, an extended version of the discrete cosine transform, and run length encoding before Lempel-Ziv-Welch coding to the proposed algorithms to improve both quality and compression rate in image compression scheme. We extensively conduct computational experiments to verify the our methods and find that the proposed algorithms achieve not only balancing the total energy consumption among sensor nodes and, thus, increasing the overall network lifetime, but also reducing block noise in image compression.

7801-7820hit(20498hit)